I2SC_SSR

I2SC Status Set Register

  0x10 32 Write-only    
Parent topic: Register Summary

I2SC Status Set Register

Bit  31 30 29 28 27 26 25 24  
                   
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
      TXURCH[1:0]          
Access      W W          
Reset      – –          
Bit  15 14 13 12 11 10 9 8  
              RXORCH[1:0]  
Access              W W  
Reset              – –  
Bit  7 6 5 4 3 2 1 0  
    TXUR       RXOR      
Access    W       W      
Reset    –       –      

Bit 2 – RXOR: Receive Overrun Status Set

Receive Overrun Status Set

Writing a ’0’ to this bit has no effect.

Writing a ’1’ to this bit sets the status bit.

Bit 6 – TXUR: Transmit Underrun Status Set

Transmit Underrun Status Set

Writing a ’0’ to this bit has no effect.

Writing a ’1’ to this bit sets the status bit.

Bits 9:8 – RXORCH[1:0]: Receive Overrun Per Channel Status Set

Receive Overrun Per Channel Status Set

Writing a ’0’ has no effect.

Writing a ’1’ to any bit in this field sets the corresponding bit in I2SC_SR and the corresponding interrupt request.

Bits 21:20 – TXURCH[1:0]: Transmit Underrun Per Channel Status Set

Transmit Underrun Per Channel Status Set

Writing a ’0’ has no effect.

Writing a ’1’ to any bit in this field sets the corresponding bit in I2SC_SR and the corresponding interrupt request.