XDMAC_GWS

XDMAC Global Channel Write Suspend Register

  0x2C 32 Read/Write 0x00000000  

XDMAC Global Channel Write Suspend Register

Bit  31 30 29 28 27 26 25 24  
                   
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
  WS23 WS22 WS21 WS20 WS19 WS18 WS17 WS16  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  
Bit  15 14 13 12 11 10 9 8  
  WS15 WS14 WS13 WS12 WS11 WS10 WS9 WS8  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  
Bit  7 6 5 4 3 2 1 0  
  WS7 WS6 WS5 WS4 WS3 WS2 WS1 WS0  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  

Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 – WSx: XDMAC Channel x Write Suspend

XDMAC Channel x Write Suspend

ValueDescription
0 The write channel is not suspended.
1

Destination requests are no longer routed to the scheduler.