AFEC_CGR

AFEC Channel Gain Register

This register can only be written if the WPEN bit is cleared in the AFEC Write Protection Mode Register.

0x54 32 Read/Write 0x00000000

AFEC Channel Gain Register
GAINx
Gain for Channel x

AFEC Channel Gain Register

Bit	31	30	29	28	27	26	25	24

Access
Reset

Bit	23	22	21	20	19	18	17	16
	GAIN11[1:0]		GAIN10[1:0]		GAIN9[1:0]		GAIN8[1:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bit	15	14	13	12	11	10	9	8
	GAIN7[1:0]		GAIN6[1:0]		GAIN5[1:0]		GAIN4[1:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bit	7	6	5	4	3	2	1	0
	GAIN3[1:0]		GAIN2[1:0]		GAIN1[1:0]		GAIN0[1:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 0:1, 2:3, 4:5, 6:7, 8:9, 10:11, 12:13, 14:15, 16:17, 18:19, 20:21, 22:23 – GAINx: Gain for Channel x

Gain for Channel x

Gain applied on input of Analog Front-End.

See section AFEC Channel Differential Register for a description of DIFFx.

GAINx	Gain Applied
GAINx	DIFFx = 0	DIFFx = 1
0	1	1
1	2	2
2	4	4
3	4	4