HSMCI Interrupt Disable Register
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Disables the corresponding interrupt.
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
UNRE | OVRE | ACKRCVE | ACKRCV | XFRDONE | FIFOEMPTY | BLKOVRE | |||
Access | |||||||||
Reset |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
CSTOE | DTOE | DCRCE | RTOE | RENDE | RCRCE | RDIRE | RINDE | ||
Access | |||||||||
Reset |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
CSRCV | SDIOWAIT | SDIOIRQA | |||||||
Access | |||||||||
Reset |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
NOTBUSY | DTIP | BLKE | TXRDY | RXRDY | CMDRDY | ||||
Access | |||||||||
Reset |
Command Ready Interrupt Disable
Receiver Ready Interrupt Disable
Transmit Ready Interrupt Disable
Data Block Ended Interrupt Disable
Data Transfer in Progress Interrupt Disable
Data Not Busy Interrupt Disable
SDIO Interrupt for Slot A Interrupt Disable
SDIO Read Wait Operation Status Interrupt Disable
Completion Signal received interrupt Disable
Response Index Error Interrupt Disable
Response Direction Error Interrupt Disable
Response CRC Error Interrupt Disable
Response End Bit Error Interrupt Disable
Response Time-out Error Interrupt Disable
Data CRC Error Interrupt Disable
Data Time-out Error Interrupt Disable
Completion Signal Time out Error Interrupt Disable
DMA Block Overrun Error Interrupt Disable
FIFO empty Interrupt Disable
Transfer Done Interrupt Disable
Boot Acknowledge Interrupt Disable
Boot Acknowledge Error Interrupt Disable
Overrun Interrupt Disable
Underrun Interrupt Disable