MCAN_IR

MCAN Interrupt Register

The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the processor clears them. A flag is cleared by writing a ‘1’ to the corresponding bit position. Writing a ‘0’ has no effect. A hard reset will clear the register. The configuration of IE controls whether an interrupt is generated. The configuration of ILS controls on which interrupt line an interrupt is signalled.

  0x50 32 Read/Write 0x00000000  
Parent topic: Register Summary

MCAN Interrupt Register

Bit  31 30 29 28 27 26 25 24  
      ARA PED PEA WDI BO EW  
Access      R/W R/W R/W R/W R/W R/W  
Reset      0 0 0 0 0 0  
Bit  23 22 21 20 19 18 17 16  
  EP ELO     DRX TOO MRAF TSW  
Access  R/W R/W     R/W R/W R/W R/W  
Reset  0 0     0 0 0 0  
Bit  15 14 13 12 11 10 9 8  
  TEFL TEFF TEFW TEFN TFE TCF TC HPM  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  
Bit  7 6 5 4 3 2 1 0  
  RF1L RF1F RF1W RF1N RF0L RF0F RF0W RF0N  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  

Bit 0 – RF0N: Receive FIFO 0 New Message

Receive FIFO 0 New Message

ValueDescription
0

No new message written to Receive FIFO 0.
1

New message written to Receive FIFO 0.

Bit 1 – RF0W: Receive FIFO 0 Watermark Reached

Receive FIFO 0 Watermark Reached

ValueDescription
0

Receive FIFO 0 fill level below watermark.
1

Receive FIFO 0 fill level reached watermark.

Bit 2 – RF0F: Receive FIFO 0 Full

Receive FIFO 0 Full

ValueDescription
0

Receive FIFO 0 not full.
1

Receive FIFO 0 full.

Bit 3 – RF0L: Receive FIFO 0 Message Lost

Receive FIFO 0 Message Lost

ValueDescription
0

No Receive FIFO 0 message lost.
1

Receive FIFO 0 message lost, also set after write attempt to Receive FIFO 0 of size zero.

Bit 4 – RF1N: Receive FIFO 1 New Message

Receive FIFO 1 New Message

ValueDescription
0

No new message written to Receive FIFO 1.
1

New message written to Receive FIFO 1.

Bit 5 – RF1W: Receive FIFO 1 Watermark Reached

Receive FIFO 1 Watermark Reached

ValueDescription
0

Receive FIFO 1 fill level below watermark.
1

Receive FIFO 1 fill level reached watermark.

Bit 6 – RF1F: Receive FIFO 1 Full

Receive FIFO 1 Full

ValueDescription
0

Receive FIFO 1 not full.
1

Receive FIFO 1 full.

Bit 7 – RF1L: Receive FIFO 1 Message Lost

Receive FIFO 1 Message Lost

ValueDescription
0

No Receive FIFO 1 message lost.
1

Receive FIFO 1 message lost, also set after write attempt to Receive FIFO 1 of size zero.

Bit 8 – HPM: High Priority Message

High Priority Message

ValueDescription
0

No high priority message received.
1

High priority message received.

Bit 9 – TC: Transmission Completed

Transmission Completed

ValueDescription
0

No transmission completed.
1

Transmission completed.

Bit 10 – TCF: Transmission Cancellation Finished

Transmission Cancellation Finished

ValueDescription
0

No transmission cancellation finished.
1

Transmission cancellation finished.

Bit 11 – TFE: Tx FIFO Empty

Tx FIFO Empty

ValueDescription
0

Tx FIFO non-empty.
1

Tx FIFO empty.

Bit 12 – TEFN: Tx Event FIFO New Entry

Tx Event FIFO New Entry

ValueDescription
0

Tx Event FIFO unchanged.
1

Tx Handler wrote Tx Event FIFO element.

Bit 13 – TEFW: Tx Event FIFO Watermark Reached

Tx Event FIFO Watermark Reached

ValueDescription
0

Tx Event FIFO fill level below watermark.
1

Tx Event FIFO fill level reached watermark.

Bit 14 – TEFF: Tx Event FIFO Full

Tx Event FIFO Full

ValueDescription
0

Tx Event FIFO not full.
1

Tx Event FIFO full.

Bit 15 – TEFL: Tx Event FIFO Element Lost

Tx Event FIFO Element Lost

ValueDescription
0

No Tx Event FIFO element lost.
1

Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero.

Bit 16 – TSW: Timestamp Wraparound

Timestamp Wraparound

ValueDescription
0

No timestamp counter wrap-around.
1

Timestamp counter wrapped around.

Bit 17 – MRAF: Message RAM Access Failure

Message RAM Access Failure

The flag is set, when the Rx Handler

• has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or message storage is aborted and the Rx Handler starts processing of the following message.

• was not able to write a message to the Message RAM. In this case message storage is aborted.

In both cases the FIFO put index is not updated resp. the New Data flag for a dedicated Receive Buffer is not set, a partly stored message is overwritten when the next message is stored to this location.

The flag is also set when the Tx Handler was not able to read a message from the Message RAM in time. In this case message transmission is aborted. In case of a Tx Handler access failure the MCAN is switched into Restricted Operation mode (see Restricted Operation Mode). To leave Restricted Operation mode, the processor has to reset MCAN_CCCR.ASM.

ValueDescription
0

No Message RAM access failure occurred.
1

Message RAM access failure occurred.

Bit 18 – TOO: Timeout Occurred

Timeout Occurred

ValueDescription
0

No timeout.
1

Timeout reached.

Bit 19 – DRX: Message stored to Dedicated Receive Buffer

Message stored to Dedicated Receive Buffer

The flag is set whenever a received message has been stored into a dedicated Receive Buffer.

ValueDescription
0

No Receive Buffer updated.
1

At least one received message stored into a Receive Buffer.

Bit 22 – ELO: Error Logging Overflow

Error Logging Overflow

ValueDescription
0

CAN Error Logging Counter did not overflow.
1

Overflow of CAN Error Logging Counter occurred.

Bit 23 – EP: Error Passive

Error Passive

ValueDescription
0

Error_Passive status unchanged.
1

Error_Passive status changed.

Bit 24 – EW: Warning Status

Warning Status

ValueDescription
0

Error_Warning status unchanged.
1

Error_Warning status changed.

Bit 25 – BO: Bus_Off Status

Bus_Off Status

ValueDescription
0

Bus_Off status unchanged.
1

Bus_Off status changed.

Bit 26 – WDI: Watchdog Interrupt

Watchdog Interrupt

ValueDescription
0

No Message RAM Watchdog event occurred.
1

Message RAM Watchdog event due to missing READY.

Bit 27 – PEA: Protocol Error in Arbitration Phase

Protocol Error in Arbitration Phase

ValueDescription
0

No protocol error in arbitration phase
1

Protocol error in arbitration phase detected (MCAN_PSR.LEC differs from 0 or 7)

Bit 28 – PED: Protocol Error in Data Phase

Protocol Error in Data Phase

ValueDescription
0

No protocol error in data phase
1

Protocol error in data phase detected (MCAN_PSR.DLEC differs from 0 or 7)

Bit 29 – ARA: Access to Reserved Address

Access to Reserved Address

ValueDescription
0

No access to reserved address occurred
1

Access to reserved address occurred