SSC_THR

SSC Transmit Holding Register

  0x24 32 Write-only –  

SSC Transmit Holding Register

Bit  31 30 29 28 27 26 25 24  
  TDAT[31:24]  
Access  W W W W W W W W  
Reset  0 0 0 0 0 0 0 0  
Bit  23 22 21 20 19 18 17 16  
  TDAT[23:16]  
Access  W W W W W W W W  
Reset  0 0 0 0 0 0 0 0  
Bit  15 14 13 12 11 10 9 8  
  TDAT[15:8]  
Access  W W W W W W W W  
Reset  0 0 0 0 0 0 0 0  
Bit  7 6 5 4 3 2 1 0  
  TDAT[7:0]  
Access  W W W W W W W W  
Reset  0 0 0 0 0 0 0  

Bits 31:0 – TDAT[31:0]: Transmit Data

Transmit Data

Right aligned regardless of the number of data bits defined by DATLEN in SSC_TFMR.