TWIHS Status Register
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| SDA | SCL | ||||||||
| Access | R | R | |||||||
| Reset | 1 | 1 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| EOSACC | SCLWS | ARBLST | NACK | ||||||
| Access | R | R | R | R | |||||
| Reset | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| UNRE | OVRE | GACC | SVACC | SVREAD | TXRDY | RXRDY | TXCOMP | ||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
Transmission Completed (cleared by writing TWIHS_THR)
0: During the length of the current frame.
1: When both holding register and internal shifter are empty and STOP condition has been sent.
TXCOMP behavior in Master mode can be seen in Master Write with One-Byte Internal Address and Multiple Data Bytes and in Master Read with Multiple Data Bytes.
0: As soon as a START is detected.
1: After a STOP or a REPEATED START + an address different from SADR is detected.
TXCOMP behavior in Slave mode can be seen in Clock Stretching in Read Mode, Clock Stretching in Write Mode, Repeated Start and Reversal from Read Mode to Write Mode and Repeated Start and Reversal from Write Mode to Read Mode.
Receive Holding Register Ready (cleared by reading TWIHS_RHR)
RXRDY behavior in Master mode can be seen in Master Read with One Data Byte, Master Read with Multiple Data Bytes and Master Read Clock Stretching with Multiple Data Bytes.
RXRDY behavior in Slave mode can be seen in Write Access Ordered by a Master, Clock Stretching in Write Mode, Repeated Start and Reversal from Read Mode to Write Mode and Repeated Start and Reversal from Write Mode to Read Mode.
| Value | Description |
|---|---|
| 0 | No character has been received since the last TWIHS_RHR read operation. |
| 1 | A byte has been received in the TWIHS_RHR since the last read. |
Transmit Holding Register Ready (cleared by writing TWIHS_THR)
0: The transmit holding register has not been transferred into the internal shifter. Set to 0 when writing into TWIHS_THR.
1: As soon as a data byte is transferred from TWIHS_THR to internal shifter or if a NACK error is detected, TXRDY is set at the same time as TXCOMP and NACK. TXRDY is also set when MSEN is set (enables TWIHS).
TXRDY behavior in Master mode can be seen in Master Write with One Data Byte, Master Write with Multiple Data Bytes and Master Write with One-Byte Internal Address and Multiple Data Bytes.
0: As soon as data is written in the TWIHS_THR, until this data has been transmitted and acknowledged (ACK or NACK).
1: Indicates that the TWIHS_THR is empty and that data has been transmitted and acknowledged.
If TXRDY is high and if a NACK has been detected, the transmission is stopped. Thus when TRDY = NACK = 1, the user must not fill TWIHS_THR to avoid losing it.
TXRDY behavior in Slave mode can be seen in Read Access Ordered by a Master, Clock Stretching in Read Mode, Repeated Start and Reversal from Read Mode to Write Mode and Repeated Start and Reversal from Write Mode to Read Mode.
Slave Read
This bit is used in Slave mode only. When SVACC is low (no slave access has been detected) SVREAD is irrelevant.
SVREAD behavior can be seen in Read Access Ordered by a Master, Clock Stretching in Read Mode, Repeated Start and Reversal from Read Mode to Write Mode and Repeated Start and Reversal from Write Mode to Read Mode.
| Value | Description |
|---|---|
| 0 | Indicates that a write access is performed by a master. |
| 1 | Indicates that a read access is performed by a master. |
Slave Access
This bit is used in Slave mode only.
SVACC behavior can be seen in Read Access Ordered by a Master, Clock Stretching in Read Mode, Repeated Start and Reversal from Read Mode to Write Mode and Repeated Start and Reversal from Write Mode to Read Mode.
| Value | Description |
|---|---|
| 0 | TWIHS is not addressed. SVACC is automatically cleared after a NACK or a STOP condition is detected. |
| 1 | Indicates that the address decoding sequence has matched (A master has sent SADR). SVACC remains high until a NACK or a STOP condition is detected. |
General Call Access (cleared on read)
This bit is used in Slave mode only.
GACC behavior can be seen in Master Performs a General Call.
| Value | Description |
|---|---|
| 0 | No general call has been detected. |
| 1 | A general call has been detected. After the detection of general call, if need be, the user may acknowledge this access and decode the following bytes and respond according to the value of the bytes. |
Overrun Error (cleared on read)
This bit is used only if clock stretching is disabled.
| Value | Description |
|---|---|
| 0 | TWIHS_RHR has not been loaded while RXRDY was set. |
| 1 | TWIHS_RHR has been loaded while RXRDY was set. Reset by read in TWIHS_SR when TXCOMP is set. |
Underrun Error (cleared on read)
This bit is used only if clock stretching is disabled.
| Value | Description |
|---|---|
| 0 | TWIHS_THR has been filled on time. |
| 1 | TWIHS_THR has not been filled on time. |
Not Acknowledged (cleared on read)
0: Each data byte has been correctly received by the far-end side TWIHS slave component.
1: A data or address byte has not been acknowledged by the slave component. Set at the same time as TXCOMP.
0: Each data byte has been correctly received by the master.
1: In Read mode, a data byte has not been acknowledged by the master. When NACK is set, the user must not fill TWIHS_THR even if TXRDY is set, because it means that the master stops the data transfer or re-initiate it.
Arbitration Lost (cleared on read)
This bit is used in Master mode only.
| Value | Description |
|---|---|
| 0 | Arbitration won. |
| 1 | Arbitration lost. Another master of the TWIHS bus has won the multimaster arbitration. TXCOMP is set at the same time. |
Clock Wait State
This bit is used in Slave mode only.
SCLWS behavior can be seen in the figures, Clock Stretching in Read Mode and Clock Stretching in Write Mode.
| Value | Description |
|---|---|
| 0 | The clock is not stretched. |
| 1 | The clock is stretched. TWIHS_THR / TWIHS_RHR buffer is not filled / emptied before the transmission / reception of a new character. |
End Of Slave Access (cleared on read)
This bit is used in Slave mode only.
EOSACC behavior can be seen in Repeated Start and Reversal from Read Mode to Write Mode and Repeated Start and Reversal from Write Mode to Read Mode.
| Value | Description |
|---|---|
| 0 | A slave access is being performing. |
| 1 | The Slave Access is finished. End Of Slave Access is automatically set as soon as SVACC is reset. |
SCL Line Value
| Value | Description |
|---|---|
| 0 | SCL line sampled value is ‘0’. |
| 1 | SCL line sampled value is ‘1.’ |
SDA Line Value
| Value | Description |
|---|---|
| 0 | SDA line sampled value is ‘0’. |
| 1 | SDA line sampled value is ‘1’. |