WDT_MR

Watchdog Timer Mode Register

The first write access prevents any further modification of the value of this register. Read accesses remain possible.

The WDT_MR register values must not be modified within three slow clock periods following a restart of the watchdog performed by a write access in WDT_CR. Any modification will cause the watchdog to trigger an end of period earlier than expected.

  0x04 32 Read/Write Once 0x3FFF2FFF  
Parent topic: Register Summary

Watchdog Timer Mode Register

Bit  31 30 29 28 27 26 25 24  
      WDIDLEHLT WDDBGHLT WDD[11:8]  
Access      R/W R/W R/W R/W R/W R/W  
Reset      1 1 1 1 1 1  
Bit  23 22 21 20 19 18 17 16  
  WDD[7:0]  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  1 1 1 1 1 1 1 1  
Bit  15 14 13 12 11 10 9 8  
  WDDIS   WDRSTEN WDFIEN WDV[11:8]  
Access  R/W   R/W R/W R/W R/W R/W R/W  
Reset  0   1 0 1 1 1 1  
Bit  7 6 5 4 3 2 1 0  
  WDV[7:0]  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  1 1 1 1 1 1 1 1  

Bits 11:0 – WDV[11:0]: Watchdog Counter Value

Watchdog Counter Value

Defines the value loaded in the 12-bit watchdog counter.

Bit 12 – WDFIEN: Watchdog Fault Interrupt Enable

Watchdog Fault Interrupt Enable

ValueDescription
0

A watchdog fault (underflow or error) has no effect on interrupt.
1

A watchdog fault (underflow or error) asserts interrupt.

Bit 13 – WDRSTEN: Watchdog Reset Enable

Watchdog Reset Enable

ValueDescription
0

A watchdog fault (underflow or error) has no effect on the resets.
1

A watchdog fault (underflow or error) triggers a watchdog reset.

Bit 15 – WDDIS: Watchdog Disable

Watchdog Disable

When setting the WDDIS bit, and while it is set, the fields WDV and WDD must not be modified.
ValueDescription
0

Enables the Watchdog Timer.
1

Disables the Watchdog Timer.

Bits 27:16 – WDD[11:0]: Watchdog Delta Value

Watchdog Delta Value

Defines the permitted range for reloading the Watchdog Timer.

If the Watchdog Timer value is less than or equal to WDD, setting bit WDT_CR.WDRSTT restarts the timer.

If the Watchdog Timer value is greater than WDD, setting bit WDT_CR.WDRSTT causes a watchdog error.

Bit 28 – WDDBGHLT: Watchdog Debug Halt

Watchdog Debug Halt

ValueDescription
0

The watchdog runs when the processor is in debug state.
1

The watchdog stops when the processor is in debug state.

Bit 29 – WDIDLEHLT: Watchdog Idle Halt

Watchdog Idle Halt

ValueDescription
0

The watchdog runs when the system is in idle state.
1

The watchdog stops when the system is in idle state.