USART Interrupt Disable Register
For SPI specific configuration, see “USART Interrupt Disable Register (SPI_MODE)”.
For LIN specific configuration, see “USART Interrupt Disable Register (LIN_MODE)”.
For LON specific configuration, see “USART Interrupt Disable Register (LON_MODE)”.
The following configuration values are valid for all listed bit names of this register:
0: No effect
1: Disables the corresponding interrupt.
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
MANE | |||||||||
Access | |||||||||
Reset |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
CTSIC | DCDIC | DSRIC | RIIC | ||||||
Access | |||||||||
Reset |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
NACK | ITER | TXEMPTY | TIMEOUT | ||||||
Access | |||||||||
Reset |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
PARE | FRAME | OVRE | RXBRK | TXRDY | RXRDY | ||||
Access | |||||||||
Reset |
RXRDY Interrupt Disable
TXRDY Interrupt Disable
Receiver Break Interrupt Disable
Overrun Error Interrupt Enable
Framing Error Interrupt Disable
Parity Error Interrupt Disable
Timeout Interrupt Disable
TXEMPTY Interrupt Disable
Max Number of Repetitions Reached Interrupt Disable
Non Acknowledge Interrupt Disable
Ring Indicator Input Change Disable
Data Set Ready Input Change Disable
Data Carrier Detect Input Change Interrupt Disable
Clear to Send Input Change Interrupt Disable
Manchester Error Interrupt Disable