QSPI_IER

QSPI Interrupt Enable Register

The following configuration values are valid for all listed bit names of this register:

0: No effect.

1: Enables the corresponding interrupt.

  0x14 32 Write-only –  
Parent topic: Register Summary

QSPI Interrupt Enable Register

Bit  31 30 29 28 27 26 25 24  
                   
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
                   
Access                   
Reset                   
Bit  15 14 13 12 11 10 9 8  
            INSTRE CSS CSR  
Access            W W W  
Reset            – – –  
Bit  7 6 5 4 3 2 1 0  
          OVRES TXEMPTY TDRE RDRF  
Access          W W W W  
Reset          – – – –  

Bit 0 – RDRF: Receive Data Register Full Interrupt Enable

Receive Data Register Full Interrupt Enable

Bit 1 – TDRE: Transmit Data Register Empty Interrupt Enable

Transmit Data Register Empty Interrupt Enable

Bit 2 – TXEMPTY: Transmission Registers Empty Enable

Transmission Registers Empty Enable

Bit 3 – OVRES: Overrun Error Interrupt Enable

Overrun Error Interrupt Enable

Bit 8 – CSR: Chip Select Rise Interrupt Enable

Chip Select Rise Interrupt Enable

Bit 9 – CSS: Chip Select Status Interrupt Enable

Chip Select Status Interrupt Enable

Bit 10 – INSTRE: Instruction End Interrupt Enable

Instruction End Interrupt Enable