HSMCI_CFG

HSMCI Configuration Register

This register can only be written if the WPEN bit is cleared in the HSMCI Write Protection Mode Register.

  0x54 32 Read/Write 0x0  

HSMCI Configuration Register

Bit  31 30 29 28 27 26 25 24  
                   
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
                   
Access                   
Reset                   
Bit  15 14 13 12 11 10 9 8  
        LSYNC       HSMODE  
Access                   
Reset        0       0  
Bit  7 6 5 4 3 2 1 0  
        FERRCTRL       FIFOMODE  
Access                   
Reset        0       0  

Bit 0 – FIFOMODE: HSMCI Internal FIFO control mode

HSMCI Internal FIFO control mode

When the block length is greater than or equal to 3/4 of the HSMCI internal FIFO size, then the write transfer starts as soon as half the FIFO is filled. When the block length is greater than or equal to half the internal FIFO size, then the write transfer starts as soon as one quarter of the FIFO is filled. In other cases, the transfer starts as soon as the total amount of data is written in the internal FIFO.

ValueDescription
0

A write transfer starts when a sufficient amount of data is written into the FIFO.

1

A write transfer starts as soon as one data is written into the FIFO.

Bit 4 – FERRCTRL: Flow Error flag reset control mode

Flow Error flag reset control mode

ValueDescription
0

When an underflow/overflow condition flag is set, a new Write/Read command is needed to reset the flag.

1

When an underflow/overflow condition flag is set, a read status resets the flag.

Bit 8 – HSMODE: High Speed Mode

High Speed Mode

ValueDescription
0

Default bus timing mode.

1

If set to one, the host controller outputs command line and data lines on the rising edge of the card clock. The Host driver shall check the high speed support in the card registers.

Bit 12 – LSYNC: Synchronize on the last block

Synchronize on the last block

ValueDescription
0

The pending command is sent at the end of the current data block.

1

The pending command is sent at the end of the block transfer when the transfer length is not infinite (block count shall be different from zero).