MLB_ACTL

AHB Control Register

The AHB Control (MLB_ACTL) register is written by the HC to configure the AHB block for channel interrupts. MLB_ACTL contains three configuration fields, one is used to select the DMA mode, one is used to multiplex channel interrupts onto a single interrupt signal, and the last selects the method of clearing channel interrupts (either software or hardware).

  0x3C0 32 Read/Write 0x00000000  
Parent topic: Register Summary

AHB Control Register

Bit  31 30 29 28 27 26 25 24  
                   
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
                   
Access                   
Reset                   
Bit  15 14 13 12 11 10 9 8  
                   
Access                   
Reset                   
Bit  7 6 5 4 3 2 1 0  
        MPB   DMA_MODE SMX SCE  
Access                   
Reset        0   0 0 0  

Bit 0 – SCE: Software Clear Enable

Software Clear Enable

ValueDescription
0 Hardware clears interrupt after a MLB_ACSRn register read
1 Software writes a ‘1’ to clear

Bit 1 – SMX: AHB Interrupt Mux Enable

AHB Interrupt Mux Enable

ValueDescription
0 MLB_ACSR0 generates an interrupt on MediaLB IRQ0; MLB_ACSR1 generates an interrupt on MediaLB IRQ1
1 MLB_ACSR0 and MLB_ACSR1 generate an interrupts on MediaLB IRQ0 only

Bit 2 – DMA_MODE: DMA Mode

DMA Mode

ValueDescription
0 DMA Mode 0
1 DMA Mode 1

Bit 4 – MPB: DMA Packet Buffering Mode

DMA Packet Buffering Mode

0 (SINGLE_PACKET): Single-packet mode

1 (MULTIPLE_PACKET): Multiple-packet mode