DMA Preview Control Register
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| P_DONE | P_IEN | P_WB | P_FETCH | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
Descriptor Fetch Control Bit
| Value | Description |
|---|---|
| 0 | Preview channel fetch operation is disabled. |
| 1 | Preview channel fetch operation is enabled. |
Descriptor Writeback Control Bit
| Value | Description |
|---|---|
| 0 | Preview channel writeback operation is disabled. |
| 1 | Preview channel writeback operation is enabled. |
Transfer Done Flag Control
| Value | Description |
|---|---|
| 0 | Preview transfer done flag generation is enabled. |
| 1 | Preview transfer done flag generation is disabled. |
Preview Transfer Done
This bit is only updated in the memory.
| Value | Description |
|---|---|
| 0 | The transfer related to this descriptor has not been performed. |
| 1 | The transfer related to this descriptor has completed. This bit is updated in memory at the end of the transfer, when writeback operation is enabled. |