MATRIX_MCFGx

Bus Matrix Master Configuration Registers

This register can only be written if the WPEN bit is cleared in the Write Protection Mode Register.

0x00 + x*0x04 [x=0..12] 32 Read/Write 0x00000000     13 4 x
Parent topic: Register Summary

Bus Matrix Master Configuration Registers

Bit  31 30 29 28 27 26 25 24  
                   
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
                   
Access                   
Reset                   
Bit  15 14 13 12 11 10 9 8  
                   
Access                   
Reset                   
Bit  7 6 5 4 3 2 1 0  
            ULBT[2:0]  
Access            R/W R/W R/W  
Reset            0 0 0  

Bits 2:0 – ULBT[2:0]: Undefined Length Burst Type

Undefined Length Burst Type

ValueNameDescription
0 UNLTD_LENGTH

Unlimited Length Burst—No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.

This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave.
1 SINGLE_ACCESS

Single Access—The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence.
2 4BEAT_BURST

4-beat Burst—The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats.
3 8BEAT_BURST

8-beat Burst—The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats.
4 16BEAT_BURST

16-beat Burst—The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats.
5 32BEAT_BURST

32-beat Burst —The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats.
6 64BEAT_BURST

64-beat Burst—The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats.
7 128BEAT_BURST

128-beat Burst—The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.

Note: Unless duly needed, the ULBT should be left at its default 0 value for power saving.