AFEC Interrupt Mask Register
The following configuration values are valid for all listed bit names of this register:
0: The corresponding interrupt is disabled.
1: The corresponding interrupt is enabled.
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
TEMPCHG | COMPE | GOVRE | DRDY | ||||||
Access | R | R | R | R | |||||
Reset | 0 | 0 | 0 | 0 |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
Access | |||||||||
Reset |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
EOC11 | EOC10 | EOC9 | EOC8 | ||||||
Access | R | R | R | R | |||||
Reset | 0 | 0 | 0 | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
EOC7 | EOC6 | EOC5 | EOC4 | EOC3 | EOC2 | EOC1 | EOC0 | ||
Access | R | R | R | R | R | R | R | R | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
End of Conversion Interrupt Mask x
Data Ready Interrupt Mask
General Overrun Error Interrupt Mask
Comparison Event Interrupt Mask
Temperature Change Interrupt Mask