USBHS_DEVIFR

Device Global Interrupt Set Register

This register always reads as zero.

The following configuration values are valid for all listed bit names of this register:

0: No effect.

1: Sets the corresponding bit in USBHS_DEVISR.

  0x000C 32 Write-only    

Device Global Interrupt Set Register

Bit  31 30 29 28 27 26 25 24  
  DMA_6 DMA_5 DMA_4 DMA_3 DMA_2 DMA_1 DMA_0    
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
                   
Access                   
Reset                   
Bit  15 14 13 12 11 10 9 8  
                   
Access                   
Reset                   
Bit  7 6 5 4 3 2 1 0  
    UPRSMS EORSMS WAKEUPS EORSTS SOFS MSOFS SUSPS  
Access                   
Reset                   

Bit 0 – SUSPS: Suspend Interrupt Set

Suspend Interrupt Set

Bit 1 – MSOFS: Micro Start of Frame Interrupt Set

Micro Start of Frame Interrupt Set

Bit 2 – SOFS: Start of Frame Interrupt Set

Start of Frame Interrupt Set

Bit 3 – EORSTS: End of Reset Interrupt Set

End of Reset Interrupt Set

Bit 4 – WAKEUPS: Wakeup Interrupt Set

Wakeup Interrupt Set

Bit 5 – EORSMS: End of Resume Interrupt Set

End of Resume Interrupt Set

Bit 6 – UPRSMS: Upstream Resume Interrupt Set

Upstream Resume Interrupt Set

Bits 25, 26, 27, 28, 29, 30, 31 – DMA_: DMA Channel x Interrupt Set

DMA Channel x Interrupt Set