TWIHS Control Register
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
FIFODIS | FIFOEN | LOCKCLR | THRCLR | ||||||
Access | W | W | W | W | |||||
Reset | – | – | – | – |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
Access | |||||||||
Reset |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
CLEAR | PECRQ | PECDIS | PECEN | SMBDIS | SMBEN | HSDIS | HSEN | ||
Access | W | W | W | W | W | W | W | W | |
Reset | – | – | – | – | – | – | – | – |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
SWRST | QUICK | SVDIS | SVEN | MSDIS | MSEN | STOP | START | ||
Access | W | W | W | W | W | W | W | W | |
Reset | – | – | – | – | – | – | – | – |
Send a START Condition
This action is necessary when the TWIHS peripheral needs to read data from a slave. When configured in Master mode with a write operation, a frame is sent as soon as the user writes a character in the Transmit Holding Register (TWIHS_THR).
Value | Description |
---|---|
0 | No effect. |
1 | A frame beginning with a START bit is transmitted according to the features defined in the TWIHS Master Mode Register (TWIHS_MMR). |
Send a STOP Condition
Value | Description |
---|---|
0 | No effect. |
1 |
STOP condition is sent just after completing the current byte transmission in Master Read mode.
|
TWIHS Master Mode Enabled
Value | Description |
---|---|
0 | No effect. |
1 | Enables the Master mode (MSDIS must be written to 0). |
TWIHS Master Mode Disabled
Value | Description |
---|---|
0 | No effect. |
1 | The Master mode is disabled, all pending data is transmitted. The shifter and holding characters (if it contains data) are transmitted in case of write operation. In read operation, the character being transferred must be completely received before disabling. |
TWIHS Slave Mode Enabled
Value | Description |
---|---|
0 | No effect. |
1 | Enables the Slave mode (SVDIS must be written to 0). |
TWIHS Slave Mode Disabled
Value | Description |
---|---|
0 | No effect. |
1 | The Slave mode is disabled. The shifter and holding characters (if it contains data) are transmitted in case of read operation. In write operation, the character being transferred must be completely received before disabling. |
SMBus Quick Command
Value | Description |
---|---|
0 | No effect. |
1 | If Master mode is enabled, a SMBus Quick Command is sent. |
Software Reset
Value | Description |
---|---|
0 | No effect. |
1 | Equivalent to a system reset. |
TWIHS High-Speed Mode Enabled
Value | Description |
---|---|
0 | No effect. |
1 | High-speed mode enabled. |
TWIHS High-Speed Mode Disabled
Value | Description |
---|---|
0 | No effect. |
1 | High-speed mode disabled. |
SMBus Mode Enabled
Value | Description |
---|---|
0 |
No effect. |
1 |
If SMBDIS = 0, SMBus mode enabled. |
SMBus Mode Disabled
Value | Description |
---|---|
0 |
No effect. |
1 |
SMBus mode disabled. |
Packet Error Checking Enable
Value | Description |
---|---|
0 |
No effect. |
1 |
SMBus PEC (CRC) generation and check enabled. |
Packet Error Checking Disable
Value | Description |
---|---|
0 |
No effect. |
1 |
SMBus PEC (CRC) generation and check disabled. |
PEC Request
Value | Description |
---|---|
0 |
No effect. |
1 |
A PEC check or transmission is requested. |
Bus CLEAR Command
Value | Description |
---|---|
0 | No effect. |
1 | If Master mode is enabled, sends a bus clear command. |
Transmit Holding Register Clear
Value | Description |
---|---|
0 | No effect. |
1 | Clears the Transmit Holding Register and sets TXRDY, TXCOMP flags. |
Lock Clear
The LOCKCLR bit is used to clear any lock scenario generated due to Error conditions of NACK, Master Code ACK Error, and SMBUS Timeout.
Any of the above error scenarios basically lock the TWIHS state machine and prevent its movement for any new transfer, no further operation occurs until the LOCK is cleared.
Value | Description |
---|---|
0 | No effect. |
1 | Clears the TWIHS FSM lock. |
FIFO Enable
Value | Description |
---|---|
0 | No effect. |
1 | Enables the Transmit and Receive FIFOs. |
FIFO Disable
Value | Description |
---|---|
0 | No effect. |
1 | Disables the Transmit and Receive FIFOs. |