TWIHS_CR

TWIHS Control Register

  0x00 32 Write-only –  

TWIHS Control Register

Bit  31 30 29 28 27 26 25 24  
      FIFODIS FIFOEN   LOCKCLR   THRCLR  
Access      W W   W   W  
Reset           
Bit  23 22 21 20 19 18 17 16  
                   
Access                   
Reset                   
Bit  15 14 13 12 11 10 9 8  
  CLEAR PECRQ PECDIS PECEN SMBDIS SMBEN HSDIS HSEN  
Access  W W W W W W W W  
Reset   
Bit  7 6 5 4 3 2 1 0  
  SWRST QUICK SVDIS SVEN MSDIS MSEN STOP START  
Access  W W W W W W W W  
Reset   

Bit 0 – START: Send a START Condition

Send a START Condition

This action is necessary when the TWIHS peripheral needs to read data from a slave. When configured in Master mode with a write operation, a frame is sent as soon as the user writes a character in the Transmit Holding Register (TWIHS_THR).

ValueDescription
0

No effect.

1

A frame beginning with a START bit is transmitted according to the features defined in the TWIHS Master Mode Register (TWIHS_MMR).

Bit 1 – STOP: Send a STOP Condition

Send a STOP Condition

ValueDescription
0

No effect.

1

STOP condition is sent just after completing the current byte transmission in Master Read mode.

  • In single data byte master read, both START and STOP must be set.
  • In multiple data bytes master read, the STOP must be set after the last data received but one.
  • In Master Read mode, if a NACK bit is received, the STOP is automatically performed.
  • In master data write operation, a STOP condition will be sent after the transmission of the current data is finished.

Bit 2 – MSEN: TWIHS Master Mode Enabled

TWIHS Master Mode Enabled

Switching from Slave to Master mode is only permitted when TXCOMP = 1.
ValueDescription
0

No effect.

1

Enables the Master mode (MSDIS must be written to 0).

Bit 3 – MSDIS: TWIHS Master Mode Disabled

TWIHS Master Mode Disabled

ValueDescription
0

No effect.

1

The Master mode is disabled, all pending data is transmitted. The shifter and holding characters (if it contains data) are transmitted in case of write operation. In read operation, the character being transferred must be completely received before disabling.

Bit 4 – SVEN: TWIHS Slave Mode Enabled

TWIHS Slave Mode Enabled

Switching from Master to Slave mode is only permitted when TXCOMP = 1.
ValueDescription
0

No effect.

1

Enables the Slave mode (SVDIS must be written to 0).

Bit 5 – SVDIS: TWIHS Slave Mode Disabled

TWIHS Slave Mode Disabled

ValueDescription
0

No effect.

1

The Slave mode is disabled. The shifter and holding characters (if it contains data) are transmitted in case of read operation. In write operation, the character being transferred must be completely received before disabling.

Bit 6 – QUICK: SMBus Quick Command

SMBus Quick Command

ValueDescription
0

No effect.

1

If Master mode is enabled, a SMBus Quick Command is sent.

Bit 7 – SWRST: Software Reset

Software Reset

ValueDescription
0

No effect.

1

Equivalent to a system reset.

Bit 8 – HSEN: TWIHS High-Speed Mode Enabled

TWIHS High-Speed Mode Enabled

ValueDescription
0

No effect.

1

High-speed mode enabled.

Bit 9 – HSDIS: TWIHS High-Speed Mode Disabled

TWIHS High-Speed Mode Disabled

ValueDescription
0

No effect.

1

High-speed mode disabled.

Bit 10 – SMBEN: SMBus Mode Enabled

SMBus Mode Enabled

ValueDescription
0

No effect.

1

If SMBDIS = 0, SMBus mode enabled.

Bit 11 – SMBDIS: SMBus Mode Disabled

SMBus Mode Disabled

ValueDescription
0

No effect.

1

SMBus mode disabled.

Bit 12 – PECEN: Packet Error Checking Enable

Packet Error Checking Enable

ValueDescription
0

No effect.

1

SMBus PEC (CRC) generation and check enabled.

Bit 13 – PECDIS: Packet Error Checking Disable

Packet Error Checking Disable

ValueDescription
0

No effect.

1

SMBus PEC (CRC) generation and check disabled.

Bit 14 – PECRQ: PEC Request

PEC Request

ValueDescription
0

No effect.

1

A PEC check or transmission is requested.

Bit 15 – CLEAR: Bus CLEAR Command

Bus CLEAR Command

ValueDescription
0

No effect.

1

If Master mode is enabled, sends a bus clear command.

Bit 24 – THRCLR: Transmit Holding Register Clear

Transmit Holding Register Clear

ValueDescription
0

No effect.

1

Clears the Transmit Holding Register and sets TXRDY, TXCOMP flags.

Bit 26 – LOCKCLR: Lock Clear

Lock Clear

The LOCKCLR bit is used to clear any lock scenario generated due to Error conditions of NACK, Master Code ACK Error, and SMBUS Timeout.

Any of the above error scenarios basically lock the TWIHS state machine and prevent its movement for any new transfer, no further operation occurs until the LOCK is cleared.

ValueDescription
0

No effect.

1

Clears the TWIHS FSM lock.

Bit 28 – FIFOEN: FIFO Enable

FIFO Enable

ValueDescription
0

No effect.

1

Enables the Transmit and Receive FIFOs.

Bit 29 – FIFODIS: FIFO Disable

FIFO Disable

ValueDescription
0

No effect.

1

Disables the Transmit and Receive FIFOs.