USB DMA Channel Transfer Descriptor

The DMA channel transfer descriptor is loaded from the memory. The following structures apply:

Offset 0:

• The address must be aligned: 0xXXXX0
• Next Descriptor Address Register: USBHS_xxxDMANXTDSCx

Offset 4:

• The address must be aligned: 0xXXXX4
• DMA Channelx Address Register: USBHS_xxxDMAADDRESSx

Offset 8:

• The address must be aligned: 0xXXXX8
• DMA Channelx Control Register: USBHS_xxxDMACONTROLx

To use the DMA channel transfer descriptor, fill the structures with the correct values (as described in the following pages), then write directly in USBHS_xxxDMANXTDSCx the address of the descriptor to be used first.

Then write 1 in the USBHS_xxxDMACONTROLx.LDNXT_DSC bit (load next channel transfer descriptor). The descriptor is automatically loaded upon pipe x / endpoint x request for packet transfer.