AES Mode Register
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
Access | |||||||||
Reset |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
CKEY[3:0] | CFBS[2:0] | ||||||||
Access | W | W | W | W | R/W | R/W | R/W | ||
Reset | 0 | 0 | 0 | – | 0 | 0 | 0 |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
LOD | OPMOD[2:0] | KEYSIZE[1:0] | SMOD[1:0] | ||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
PROCDLY[3:0] | DUALBUFF | GTAGEN | CIPHER | ||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Processing Mode
Value | Description |
---|---|
0 | Decrypts data. |
1 | Encrypts data. |
GCM Automatic Tag Generation Enable
Value | Description |
---|---|
0 | Automatic GCM Tag generation disabled. |
1 | Automatic GCM Tag generation enabled. |
Dual Input Buffer
Value | Name | Description |
---|---|---|
0 | INACTIVE |
AES_IDATARx cannot be written during processing of previous block. |
1 | ACTIVE |
AES_IDATARx can be written during processing of previous block when SMOD = 2. It speeds up the overall runtime of large files. |
Processing Delay
Processing Time = N × (PROCDLY + 1)
where
The processing time represents the number of clock cycles that the AES needs in order to perform one encryption/decryption.
Start Mode
If a DMA transfer is used, configure SMOD to 2. See DMA Mode for more details.
Value | Name | Description |
---|---|---|
0 | MANUAL_START | Manual Mode |
1 | AUTO_START | Auto Mode |
2 | IDATAR0_START | AES_IDATAR0 access only Auto Mode (DMA) |
Key Size
Value | Name | Description |
---|---|---|
0 | AES128 |
AES Key Size is 128 bits |
1 | AES192 |
AES Key Size is 192 bits |
2 | AES256 |
AES Key Size is 256 bits |
Operating Mode
For CBC-MAC operating mode, set OPMOD to CBC and LOD to 1.
Value | Name | Description |
---|---|---|
0 | ECB | ECB: Electronic Codebook mode |
1 | CBC | CBC: Cipher Block Chaining mode |
2 | OFB | OFB: Output Feedback mode |
3 | CFB | CFB: Cipher Feedback mode |
4 | CTR | CTR: Counter mode (16-bit internal counter) |
5 | GCM |
GCM: Galois/Counter mode |
Last Output Data Mode
Value | Description |
---|---|
0 | No effect. After each end of encryption/decryption, the output data are available either on the output data registers (Manual and Auto modes) or at the address specified in the Channel Buffer Transfer Descriptor for DMA mode. In Manual and Auto modes, the DATRDY flag is cleared when at least one of the Output Data registers is read. |
1 | The DATRDY flag is cleared when at least one of the Input Data Registers is written. No more Output Data Register reads are necessary between consecutive encryptions/decryptions (see Last Output Data Mode). |
Cipher Feedback Data Size
Value | Name | Description |
---|---|---|
0 | SIZE_128BIT | 128-bit |
1 | SIZE_64BIT | 64-bit |
2 | SIZE_32BIT | 32-bit |
3 | SIZE_16BIT | 16-bit |
4 | SIZE_8BIT | 8-bit |
Key
Value | Name | Description |
---|---|---|
0xE | PASSWD | This field must be written with 0xE the first time AES_MR is programmed. For subsequent programming of AES_MR, any value can be written, including that of 0xE. Always reads as 0. |