SPI Mode Register
This register can only be written if the WPEN bit is cleared in theSPI Write Protection Mode Register .
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| DLYBCS[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| PCS[3:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| LLB | WDRBT | MODFDIS | PCSDEC | PS | MSTR | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
Master/Slave Mode
| Value | Description |
|---|---|
| 0 | SPI is in Slave mode |
| 1 | SPI is in Master mode |
Peripheral Select
| Value | Description |
|---|---|
| 0 | Fixed Peripheral Select |
| 1 | Variable Peripheral Select |
Chip Select Decode
When PCSDEC = 1, up to 15 chip select signals can be generated with the four NPCS lines using an external 4-bit to 16-bit decoder. The chip select registers define the characteristics of the 15 chip selects, with the following rules:
SPI_CSR0 defines peripheral chip select signals 0 to 3.
SPI_CSR1 defines peripheral chip select signals 4 to 7.
SPI_CSR2 defines peripheral chip select signals 8 to 11.
SPI_CSR3 defines peripheral chip select signals 12 to 14.
| Value | Description |
|---|---|
| 0 | The chip select lines are directly connected to a peripheral device. |
| 1 | The four NPCS chip select lines are connected to a 4-bit to 16-bit decoder. |
Mode Fault Detection
| Value | Description |
|---|---|
| 0 | Mode fault detection enabled |
| 1 | Mode fault detection disabled |
Wait Data Read Before Transfer
| Value | Description |
|---|---|
| 0 | No Effect. In Master mode, a transfer can be initiated regardless of SPI_RDR state. |
| 1 | In Master mode, a transfer can start only if SPI_RDR is empty, i.e., does not contain any unread data. This mode prevents overrun error in reception. |
Local Loopback Enable
LLB controls the local loopback on the data shift register for testing in Master mode only (MISO is internally connected on MOSI).
| Value | Description |
|---|---|
| 0 | Local loopback path disabled. |
| 1 | Local loopback path enabled. |
Peripheral Chip Select
This field is only used if fixed peripheral select is active (PS = 0).
If SPI_MR.PCSDEC = 0:
PCS = xxx0 NPCS[3:0] = 1110
PCS = xx01 NPCS[3:0] = 1101
PCS = x011 NPCS[3:0] = 1011
PCS = 0111 NPCS[3:0] = 0111
PCS = 1111 forbidden (no peripheral is selected)
(x = don’t care)
If SPI_MR.PCSDEC = 1:
NPCS[3:0] output signals = PCS.
Delay Between Chip Selects
This field defines the delay between the inactivation and the activation of NPCS. The DLYBCS time guarantees nonoverlapping chip selects and solves bus contentions in case of peripherals having long data float times.
If DLYBCS is lower than 6, six peripheral clock periods are inserted by default.
Otherwise, the following equation determines the delay: