Device Global Interrupt Enable Register
This register always reads as zero.
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Sets the corresponding bit in USBHS_DEVIMR.
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
DMA_6 | DMA_5 | DMA_4 | DMA_3 | DMA_2 | DMA_1 | DMA_0 | |||
Access | |||||||||
Reset |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
PEP_9 | PEP_8 | PEP_7 | PEP_6 | PEP_5 | PEP_4 | ||||
Access | |||||||||
Reset |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
PEP_3 | PEP_2 | PEP_1 | PEP_0 | ||||||
Access | |||||||||
Reset |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
UPRSMES | EORSMES | WAKEUPES | EORSTES | SOFES | MSOFES | SUSPES | |||
Access | |||||||||
Reset |
Suspend Interrupt Enable
Micro Start of Frame Interrupt Enable
Start of Frame Interrupt Enable
End of Reset Interrupt Enable
Wakeup Interrupt Enable
End of Resume Interrupt Enable
Upstream Resume Interrupt Enable
Endpoint x Interrupt Enable
DMA Channel x Interrupt Enable