MCAN_TXBTIE

MCAN Transmit Buffer Transmission Interrupt Enable

  0xE0 32 Read/Write 0x00000000  
Parent topic: Register Summary

MCAN Transmit Buffer Transmission Interrupt Enable

Bit  31 30 29 28 27 26 25 24  
  TIE31 TIE30 TIE29 TIE28 TIE27 TIE26 TIE25 TIE24  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  
Bit  23 22 21 20 19 18 17 16  
  TIE23 TIE22 TIE21 TIE20 TIE19 TIE18 TIE17 TIE16  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  
Bit  15 14 13 12 11 10 9 8  
  TIE15 TIE14 TIE13 TIE12 TIE11 TIE10 TIE9 TIE8  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  
Bit  7 6 5 4 3 2 1 0  
  TIE7 TIE6 TIE5 TIE4 TIE3 TIE2 TIE1 TIE0  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  

Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – TIEx: Transmission Interrupt Enable for Buffer x

Transmission Interrupt Enable for Buffer x

Each Transmit Buffer has its own Transmission Interrupt Enable bit.

ValueDescription
0

Transmission interrupt disabled
1

Transmission interrupt enable