TC_IERx

TC Interrupt Enable Register

The following configuration values are valid for all listed bit names of this register:

0: No effect.

1: Enables the corresponding interrupt.

  0x24 + x*0x40 [x=0..2] 32 Write-only –   3 64 -1
Parent topic: Register Summary

TC Interrupt Enable Register

Bit  31 30 29 28 27 26 25 24  
                   
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
                   
Access                   
Reset                   
Bit  15 14 13 12 11 10 9 8  
                   
Access                   
Reset                   
Bit  7 6 5 4 3 2 1 0  
  ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS  
Access  W W W W W W W W  
Reset  – – – – – – – –  

Bit 0 – COVFS: Counter Overflow

Counter Overflow

Bit 1 – LOVRS: Load Overrun

Load Overrun

Bit 2 – CPAS: RA Compare

RA Compare

Bit 3 – CPBS: RB Compare

RB Compare

Bit 4 – CPCS: RC Compare

RC Compare

Bit 5 – LDRAS: RA Loading

RA Loading

Bit 6 – LDRBS: RB Loading

RB Loading

Bit 7 – ETRGS: External Trigger

External Trigger