GMAC_IMR

GMAC Interrupt Mask Register

This register is a read-only register indicating which interrupts are masked. All bits are set at Reset and can be reset individually by writing to the Interrupt Enable Register (GMAC_IER), or set individually by writing to the Interrupt Disable Register (GMAC_IDR).

For test purposes there is a write-only function to this register that allows the bits in the Interrupt Status Register to be set or cleared, regardless of the state of the mask register. A write to this register directly affects the state of the corresponding bit in the Interrupt Status Register, causing an interrupt to be generated if a 1 is written.

The following values are valid for all listed bit names of this register when read:

0: The corresponding interrupt is enabled.

1: The corresponding interrupt is not enabled.

  0x030 32 Read/Write 0x07FFFFFF  
Parent topic: Register Summary

GMAC Interrupt Mask Register

Bit  31 30 29 28 27 26 25 24  
      TSUTIMCMP WOL RXLPISBC SRI PDRSFT PDRQFT  
Access      R/W R/W R/W R/W R/W R/W  
Reset      0 0 0 1 1 1  
Bit  23 22 21 20 19 18 17 16  
  PDRSFR PDRQFR SFT DRQFT SFR DRQFR      
Access  R/W R/W R/W R/W R/W R/W      
Reset  1 1 1 1 1 1      
Bit  15 14 13 12 11 10 9 8  
  EXINT PFTR PTZ PFNZ HRESP ROVR      
Access  R/W R/W R/W R/W R/W R/W      
Reset  1 1 1 1 1 1      
Bit  7 6 5 4 3 2 1 0  
  TCOMP TFC RLEX TUR TXUBR RXUBR RCOMP MFS  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  1 1 1 1 1 1 1 1  

Bit 0 – MFS: Management Frame Sent

Management Frame Sent

Bit 1 – RCOMP: Receive Complete

Receive Complete

Bit 2 – RXUBR: RX Used Bit Read

RX Used Bit Read

Bit 3 – TXUBR: TX Used Bit Read

TX Used Bit Read

Bit 4 – TUR: Transmit Underrun

Transmit Underrun

Bit 5 – RLEX: Retry Limit Exceeded

Retry Limit Exceeded

Bit 6 – TFC: Transmit Frame Corruption Due to AHB Error

Transmit Frame Corruption Due to AHB Error

Bit 7 – TCOMP: Transmit Complete

Transmit Complete

Bit 10 – ROVR: Receive Overrun

Receive Overrun

Bit 11 – HRESP: HRESP Not OK

HRESP Not OK

Bit 12 – PFNZ: Pause Frame with Non-zero Pause Quantum Received

Pause Frame with Non-zero Pause Quantum Received

Bit 13 – PTZ: Pause Time Zero

Pause Time Zero

Bit 14 – PFTR: Pause Frame Transmitted

Pause Frame Transmitted

Bit 15 – EXINT: External Interrupt

External Interrupt

Bit 18 – DRQFR: PTP Delay Request Frame Received

PTP Delay Request Frame Received

Bit 19 – SFR: PTP Sync Frame Received

PTP Sync Frame Received

Bit 20 – DRQFT: PTP Delay Request Frame Transmitted

PTP Delay Request Frame Transmitted

Bit 21 – SFT: PTP Sync Frame Transmitted

PTP Sync Frame Transmitted

Bit 22 – PDRQFR: PDelay Request Frame Received

PDelay Request Frame Received

Bit 23 – PDRSFR: PDelay Response Frame Received

PDelay Response Frame Received

Bit 24 – PDRQFT: PDelay Request Frame Transmitted

PDelay Request Frame Transmitted

Bit 25 – PDRSFT: PDelay Response Frame Transmitted

PDelay Response Frame Transmitted

Bit 26 – SRI: TSU Seconds Register Increment

TSU Seconds Register Increment

Bit 27 – RXLPISBC: Receive LPI indication Status Bit Change

Receive LPI indication Status Bit Change

Receive LPI indication status bit change.

Cleared on read.

Bit 28 – WOL: Wake On LAN

Wake On LAN

Bit 29 – TSUTIMCMP: TSU Timer Comparison

TSU Timer Comparison