SSC_CMR

SSC Clock Mode Register

This register can only be written if the WPEN bit is cleared in the SSC Write Protection Mode Register.

  0x4 32 Read/Write 0x00000000  

SSC Clock Mode Register

Bit  31 30 29 28 27 26 25 24  
                   
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
                   
Access                   
Reset                   
Bit  15 14 13 12 11 10 9 8  
          DIV[11:8]  
Access          R/W R/W R/W R/W  
Reset          0 0 0 0  
Bit  7 6 5 4 3 2 1 0  
  DIV[7:0]  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  

Bits 11:0 – DIV[11:0]: Clock Divider

Clock Divider

ValueDescription
0

The Clock Divider is not active.

Any other value The divided clock equals the peripheral clock divided by 2 times DIV.
The maximum bit rate is fperipheral clock/2. The minimum bit rate is fperipheral clock/2 × 4095 = fperipheral clock/8190.