Host Global Interrupt Disable Register
This register always reads as zero.
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Clears the corresponding bit in USBHS_HSTIMR.
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
DMA_6 | DMA_5 | DMA_4 | DMA_3 | DMA_2 | DMA_1 | DMA_0 | |||
Access | |||||||||
Reset |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
PEP_9 | PEP_8 | ||||||||
Access | |||||||||
Reset |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
PEP_7 | PEP_6 | PEP_5 | PEP_4 | PEP_3 | PEP_2 | PEP_1 | PEP_0 | ||
Access | |||||||||
Reset |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
HWUPIEC | HSOFIEC | RXRSMIEC | RSMEDIEC | RSTIEC | DDISCIEC | DCONNIEC | |||
Access | |||||||||
Reset |
Device Connection Interrupt Disable
Device Disconnection Interrupt Disable
USB Reset Sent Interrupt Disable
Downstream Resume Sent Interrupt Disable
Upstream Resume Received Interrupt Disable
Host Start of Frame Interrupt Disable
Host Wakeup Interrupt Disable
Pipe x Interrupt Disable
DMA Channel x Interrupt Disable