XDMAC_GRWR

XDMAC Global Channel Read Write Resume Register

  0x34 32 Write-only –  
Parent topic: Register Summary

XDMAC Global Channel Read Write Resume Register

Bit  31 30 29 28 27 26 25 24  
                   
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
  RWR23 RWR22 RWR21 RWR20 RWR19 RWR18 RWR17 RWR16  
Access  W W W W W W W W  
Reset  – – – – – – – –  
Bit  15 14 13 12 11 10 9 8  
  RWR15 RWR14 RWR13 RWR12 RWR11 RWR10 RWR9 RWR8  
Access  W W W W W W W W  
Reset  – – – – – – – –  
Bit  7 6 5 4 3 2 1 0  
  RWR7 RWR6 RWR5 RWR4 RWR3 RWR2 RWR1 RWR0  
Access  W W W W W W W W  
Reset  – – – – – – – –  

Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 – RWRx: XDMAC Channel x Read Write Resume

XDMAC Channel x Read Write Resume

ValueDescription
0

No effect.
1

Read and write requests are serviced.