SPI_IMR

SPI Interrupt Mask Register

The following configuration values are valid for all listed bit names of this register:

0: The corresponding interrupt is not enabled.

1: The corresponding interrupt is enabled.

  0x1C 32 Read-only 0x0  
Parent topic: Register Summary

SPI Interrupt Mask Register

Bit  31 30 29 28 27 26 25 24  
                   
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
                   
Access                   
Reset                   
Bit  15 14 13 12 11 10 9 8  
            UNDES TXEMPTY NSSR  
Access            R R R  
Reset            0 0 0  
Bit  7 6 5 4 3 2 1 0  
          OVRES MODF TDRE RDRF  
Access          R R R R  
Reset          0 0 0 0  

Bit 0 – RDRF: Receive Data Register Full Interrupt Mask

Receive Data Register Full Interrupt Mask

Bit 1 – TDRE: SPI Transmit Data Register Empty Interrupt Mask

SPI Transmit Data Register Empty Interrupt Mask

Bit 2 – MODF: Mode Fault Error Interrupt Mask

Mode Fault Error Interrupt Mask

Bit 3 – OVRES: Overrun Error Interrupt Mask

Overrun Error Interrupt Mask

Bit 8 – NSSR: NSS Rising Interrupt Mask

NSS Rising Interrupt Mask

Bit 9 – TXEMPTY: Transmission Registers Empty Mask

Transmission Registers Empty Mask

Bit 10 – UNDES: Underrun Error Interrupt Mask

Underrun Error Interrupt Mask