Timings are given for the 3.3V domain, with VDDIO from 2.85V to 3.6V, maximum external capacitor = 40 pF.
| Symbol | Parameter | Conditions | Min | Max | Unit |
|---|---|---|---|---|---|
| SPI0 | MISO Setup time before SPCK rises (master) | 3.3V domain | 12.4 | – | ns |
| SPI1 | MISO Hold time after SPCK rises (master) | 3.3V domain | 0 | – | ns |
| SPI2 | SPCK rising to MOSI Delay (master) | 3.3V domain | -3.7 | 2.2 | ns |
| SPI3 | MISO Setup time before SPCK falls (master) | 3.3V domain | 12.6 | – | ns |
| SPI4 | MISO Hold time after SPCK falls (master) | 3.3V domain | 0 | – | ns |
| SPI5 | SPCK falling to MOSI Delay (master) | 3.3V domain | -3.6 | 2.0 | ns |
| SPI6 | SPCK falling to MISO Delay (slave) | 3.3V domain | 3.0 | 11.9 | ns |
| SPI7 | MOSI Setup time before SPCK rises (slave) | 3.3V domain | 1.2 | – | ns |
| SPI8 | MOSI Hold time after SPCK rises (slave) | 3.3V domain | 0.6 | – | ns |
| SPI9 | SPCK rising to MISO Delay (slave) | 3.3V domain | 3.0 | 12.0 | ns |
| SPI10 | MOSI Setup time before SPCK falls (slave) | 3.3V domain | 1.2 | – | ns |
| SPI11 | MOSI Hold time after SPCK falls (slave) | 3.3V domain | 0.6 | – | ns |
| SPI12 | NPCS setup to SPCK rising (slave) | 3.3V domain | 3.9 | – | ns |
| SPI13 | NPCS hold after SPCK falling (slave) | 3.3V domain | 0 | – | ns |
| SPI14 | NPCS setup to SPCK falling (slave) | 3.3V domain | 4.0 | – | ns |
| SPI15 | NPCS hold after SPCK falling (slave) | 3.3V domain | 0 | – | ns |
Note that in SPI master mode, the device does not sample the data (MISO) on the opposite edge where the data clocks out (MOSI), but the same edge is used. See Figure 1 and Figure 2.