RTC_IMR

RTC Interrupt Mask Register

  0x28 32 Read-only 0x00000000  
Parent topic: Register Summary

RTC Interrupt Mask Register

Bit  31 30 29 28 27 26 25 24  
                   
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
                   
Access                   
Reset                   
Bit  15 14 13 12 11 10 9 8  
                   
Access                   
Reset                   
Bit  7 6 5 4 3 2 1 0  
      TDERR CAL TIM SEC ALR ACK  
Access      R R R R R R  
Reset      0 0 0 0 0 0  

Bit 0 – ACK: Acknowledge Update Interrupt Mask

Acknowledge Update Interrupt Mask

ValueDescription
0

The acknowledge for update interrupt is disabled.
1

The acknowledge for update interrupt is enabled.

Bit 1 – ALR: Alarm Interrupt Mask

Alarm Interrupt Mask

ValueDescription
0

The alarm interrupt is disabled.
1

The alarm interrupt is enabled.

Bit 2 – SEC: Second Event Interrupt Mask

Second Event Interrupt Mask

ValueDescription
0

The second periodic interrupt is disabled.
1

The second periodic interrupt is enabled.

Bit 3 – TIM: Time Event Interrupt Mask

Time Event Interrupt Mask

ValueDescription
0

The selected time event interrupt is disabled.
1

The selected time event interrupt is enabled.

Bit 4 – CAL: Calendar Event Interrupt Mask

Calendar Event Interrupt Mask

ValueDescription
0

The selected calendar event interrupt is disabled.
1

The selected calendar event interrupt is enabled.

Bit 5 – TDERR: Time and/or Date Error Mask

Time and/or Date Error Mask

ValueDescription
0

The time and/or date error event is disabled.
1

The time and/or date error event is enabled.