Host Pipe x Status Register (Control, Bulk Pipes)
This register view is relevant only if PTYPE = 0x0 or 0x2 in ”Host Pipe x Configuration Register”.
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| PBYCT[10:4] | |||||||||
| Access | |||||||||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| PBYCT[3:0] | CFGOK | RWALL | |||||||
| Access | |||||||||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| CURRBK[1:0] | NBUSYBK[1:0] | DTSEQ[1:0] | |||||||
| Access | |||||||||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SHORTPACKETI | RXSTALLDI | OVERFI | NAKEDI | PERRI | TXSTPI | TXOUTI | RXINI | ||
| Access | |||||||||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Received IN Data Interrupt
| Value | Description |
|---|---|
| 0 | Cleared when USBHS_HSTPIPICR.RXINIC = 1. |
| 1 | Set when a new USB message is stored in the current bank of the pipe. This triggers an interrupt if USBHS_HSTPIPIMR.RXINE = 1. |
Transmitted OUT Data Interrupt
| Value | Description |
|---|---|
| 0 | Cleared when USBHS_HSTPIPICR.TXOUTIC = 1. |
| 1 | Set when the current OUT bank is free and can be filled. This triggers an interrupt if USBHS_HSTPIPIMR.TXOUTE = 1. |
Transmitted SETUP Interrupt
| Value | Description |
|---|---|
| 0 | Cleared when USBHS_HSTPIPICR.TXSTPIC = 1. |
| 1 | Set, for control pipes, when the current SETUP bank is free and can be filled. This triggers an interrupt if USBHS_HSTPIPIMR.TXSTPE = 1. |
Pipe Error Interrupt
| Value | Description |
|---|---|
| 0 | Cleared when the error source bit is cleared. |
| 1 | Set when an error occurs on the current bank of the pipe. This triggers an interrupt if the USBHS_HSTPIPIMR.PERRE bit is set. Refer to the USBHS_HSTPIPERRx register to determine the source of the error. |
NAKed Interrupt
| Value | Description |
|---|---|
| 0 | Cleared when USBHS_HSTPIPICR.NAKEDIC = 1. |
| 1 | Set when a NAK has been received on the current bank of the pipe. This triggers an interrupt if USBHS_HSTPIPIMR.NAKEDE = 1. |
Overflow Interrupt
| Value | Description |
|---|---|
| 0 | Cleared when USBHS_HSTPIPICR.OVERFIC = 1. |
| 1 | Set when the current pipe has received more data than the maximum length of the current pipe. An interrupt is triggered if USBHS_HSTPIPIMR.OVERFIE = 1. |
Received STALLed Interrupt
This bit is set when a STALL handshake has been received on the current bank of the pipe. The pipe is automatically frozen. This triggers an interrupt if USBHS_HSTPIPIMR.RXSTALLE = 1.
| Value | Description |
|---|---|
| 0 | Cleared when USBHS_HSTPIPICR.RXSTALLDIC = 1. |
Short Packet Interrupt
| Value | Description |
|---|---|
| 0 | Cleared when USBHS_HSTPIPICR.SHORTPACKETIC = 1. |
| 1 | Set when a short packet is received by the host controller (packet length inferior to the PSIZE programmed field). |
Data Toggle Sequence
This field indicates the data PID of the current bank.
For an OUT pipe, this field indicates the data toggle of the next packet that is to be sent.
For an IN pipe, this field indicates the data toggle of the received packet stored in the current bank.
| Value | Name | Description |
|---|---|---|
| 0 | DATA0 | Data0 toggle sequence |
| 1 | DATA1 | Data1 toggle sequence |
| 2 | Reserved |
|
| 3 | Reserved |
Number of Busy Banks
This field indicates the number of busy banks.
For an OUT pipe, this field indicates the number of busy banks, filled by the user, ready for OUT transfer. When all banks are busy, this triggers a PEP_x interrupt if USBHS_HSTPIPIMRx.NBUSYBKE = 1.
For an IN pipe, this field indicates the number of busy banks filled by IN transaction from the Device. When all banks are free, this triggers a PEP_x interrupt if USBHS_HSTPIPIMRx.NBUSYBKE = 1.
| Value | Name | Description |
|---|---|---|
| 0 | 0_BUSY | 0 busy bank (all banks free) |
| 1 | 1_BUSY | 1 busy bank |
| 2 | 2_BUSY | 2 busy banks |
| 3 | 3_BUSY | 3 busy banks |
Current Bank
For non-control pipe, this field indicates the number of the current bank.
This field may be updated 1 clock cycle after the RWALL bit changes, so the user should not poll it as an interrupt bit.
| Value | Name | Description |
|---|---|---|
| 0 | BANK0 | Current bank is bank0 |
| 1 | BANK1 | Current bank is bank1 |
| 2 | BANK2 | Current bank is bank2 |
| 3 | Reserved |
Read/Write Allowed
For an OUT pipe, this bit is set when the current bank is not full, i.e., the software can write further data into the FIFO.
For an IN pipe, this bit is set when the current bank is not empty, i.e., the software can read further data from the FIFO.
This bit is cleared otherwise.
This bit is also cleared when the RXSTALLDI or the PERRI bit = 1.
Configuration OK Status
This bit is set/cleared when the USBHS_HSTPIPCFGx.ALLOC bit is set.
This bit is set if the pipe x number of banks (USBHS_HSTPIPCFGx.PBK) and size (USBHS_HSTPIPCFGx.PSIZE) are correct compared to the maximal allowed number of banks and size for this pipe and to the maximal FIFO size (i.e., the DPRAM size).
If this bit is cleared, the user should rewrite correct values for the PBK and PSIZE fields in the USBHS_HSTPIPCFGx register.
Pipe Byte Count
This field contains the byte count of the FIFO.
For an OUT pipe, the field is incremented after each byte written by the user into the pipe and decremented after each byte sent to the peripheral.
For an IN pipe, the field is incremented after each byte received from the peripheral and decremented after each byte read by the user from the pipe.
This field may be updated 1 clock cycle after the RWALL bit changes, so the user should not poll this field as an interrupt bit.