MCAN_NDAT1

MCAN New Data 1

  0x98 32 Read/Write 0x00000000  

MCAN New Data 1

Bit  31 30 29 28 27 26 25 24  
  ND31 ND30 ND29 ND28 ND27 ND26 ND25 ND24  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  
Bit  23 22 21 20 19 18 17 16  
  ND23 ND22 ND21 ND20 ND19 ND18 ND17 ND16  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  
Bit  15 14 13 12 11 10 9 8  
  ND15 ND14 ND13 ND12 ND11 ND10 ND9 ND8  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  
Bit  7 6 5 4 3 2 1 0  
  ND7 ND6 ND5 ND4 ND3 ND2 ND1 ND0  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  

Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – NDx: New Data

New Data

The register holds the New Data flags of Receive Buffers 0 to 31. The flags are set when the respective Receive Buffer has been updated from a received frame. The flags remain set until the processor clears them. A flag is cleared by writing a ‘1’ to the corresponding bit position. Writing a ‘0’ has no effect. A hard reset will clear the register.

ValueDescription
0

Receive Buffer not updated

1

Receive Buffer updated from new message