PIO_PCIMR

PIO Parallel Capture Interrupt Mask Register

The following configuration values are valid for all listed bit names of this register:

0: Corresponding interrupt is not enabled.

1: Corresponding interrupt is enabled.

  0x015C 32 Read-only 0x00000000  
Parent topic: Parallel Input/Output Controller (PIO) User Interface

PIO Parallel Capture Interrupt Mask Register

Bit  31 30 29 28 27 26 25 24  
                   
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
                   
Access                   
Reset                   
Bit  15 14 13 12 11 10 9 8  
                   
Access                   
Reset                   
Bit  7 6 5 4 3 2 1 0  
          RXBUFF ENDRX OVRE DRDY  
Access                   
Reset          0 0 0 0  

Bit 0 – DRDY: Parallel Capture Mode Data Ready Interrupt Mask

Parallel Capture Mode Data Ready Interrupt Mask

Bit 1 – OVRE: Parallel Capture Mode Overrun Error Interrupt Mask

Parallel Capture Mode Overrun Error Interrupt Mask

Bit 2 – ENDRX: End of Reception Transfer Interrupt Mask

End of Reception Transfer Interrupt Mask

Bit 3 – RXBUFF: Reception Buffer Full Interrupt Mask

Reception Buffer Full Interrupt Mask