XDMAC_CDA

XDMAC Channel x Destination Address Register [x = 0..23]

  0x64 + n*0x40 [n=0..23] 32 Read/Write 0x00000000   24 64
Parent topic: Register Summary

XDMAC Channel x Destination Address Register [x = 0..23]

Bit  31 30 29 28 27 26 25 24  
  DA[31:24]  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  
Bit  23 22 21 20 19 18 17 16  
  DA[23:16]  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  
Bit  15 14 13 12 11 10 9 8  
  DA[15:8]  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  
Bit  7 6 5 4 3 2 1 0  
  DA[7:0]  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  

Bits 31:0 – DA[31:0]: Channel x Destination Address

Channel x Destination Address

Program this register with the destination address of the DMA transfer.

A configuration error is generated when this address is not aligned with the transfer data size.