PWM_DTUPDx

PWM Channel Dead Time Update Register

This register can only be written if bits WPSWS4 and WPHWS4 are cleared in the PWM Write Protection Status Register.

This register acts as a double buffer for the DTH and DTL values. This prevents an unexpected waveform when modifying the dead-time values.

Only the first 12 bits (dead-time counter size) of fields DTHUPD and DTLUPD are significant.

  0x021C + x*0x20 [x=0..3] 32 Write-only 0x00000000   4 32 -1

PWM Channel Dead Time Update Register

Bit  31 30 29 28 27 26 25 24  
  DTLUPD[15:8]  
Access  W W W W W W W W  
Reset  0 0 0 0 0 0 0 0  
Bit  23 22 21 20 19 18 17 16  
  DTLUPD[7:0]  
Access  W W W W W W W W  
Reset  0 0 0 0 0 0 0  
Bit  15 14 13 12 11 10 9 8  
  DTHUPD[15:8]  
Access  W W W W W W W W  
Reset  0 0 0 0 0 0 0 0  
Bit  7 6 5 4 3 2 1 0  
  DTHUPD[7:0]  
Access  W W W W W W W W  
Reset  0 0 0 0 0 0 0  

Bits 15:0 – DTHUPD[15:0]: Dead-Time Value Update for PWMHx Output

Dead-Time Value Update for PWMHx Output

Defines the dead-time value for PWMHx output. This value must be defined between 0 and the value (CPRD – CDTY) (PWM_CPRDx and PWM_CDTYx). This value is applied only at the beginning of the next channel x PWM period.

Bits 31:16 – DTLUPD[15:0]: Dead-Time Value Update for PWMLx Output

Dead-Time Value Update for PWMLx Output

Defines the dead-time value for PWMLx output. This value must be defined between 0 and CDTY (PWM_CDTYx). This value is applied only at the beginning of the next channel x PWM period.