The USB High-Speed Interface (USBHS) complies with the Universal Serial Bus (USB) 2.0 specification in all speeds.
Each pipe/endpoint can be configured in one of several USB transfer types. It can be associated with one, two or three banks of a DPRAM used to store the current data payload. If two or three banks are used, then one DPRAM bank is read or written by the CPU or the DMA, while the other is read or written by the USBHS core. This feature is mandatory for isochronous pipes/endpoints.
The following table describes the hardware configuration of the USB MCU device.
| Pipe/Endpoint | Mnemonic | Max. Number Banks | DMA | High Band Width | Max. Pipe/ Endpoint Size | Type |
|---|---|---|---|---|---|---|
| 0 | PEP_0 | 1 | N | N | 64 | Control |
| 1 | PEP_1 | 3 | Y | Y | 1024 | Isochronous/Bulk/Interrupt/Control |
| 2 | PEP_2 | 3 | Y | Y | 1024 | Isochronous/Bulk/Interrupt/Control |
| 3 | PEP_3 | 2 | Y | Y | 1024 | Isochronous/Bulk/Interrupt/Control |
| 4 | PEP_4 | 2 | Y | Y | 1024 | Isochronous/Bulk/Interrupt/Control |
| 5 | PEP_5 | 2 | Y | Y | 1024 | Isochronous/Bulk/Interrupt/Control |
| 6 | PEP_6 | 2 | Y | Y | 1024 | Isochronous/Bulk/Interrupt/Control |
| 7 | PEP_7 | 2 | Y | Y | 1024 | Isochronous/Bulk/Interrupt/Control |
| 8 | PEP_8 | 2 | N | Y | 1024 | Isochronous/Bulk/Interrupt/Control |
| 9 | PEP_9 | 2 | N | Y | 1024 | Isochronous/Bulk/Interrupt/Control |