The Write mode is defined as a data transmission from the master.
After a START or a REPEATED START, the decoding of the address starts. If the slave address is decoded, SVACC is set and SVREAD indicates the direction of the transfer (SVREAD is low in this case).
Until a STOP or REPEATED START condition is detected, the TWIHS stores the received data in TWIHS_RHR.
If a STOP condition or a REPEATED START + an address different from SADR is detected, SVACC is reset.
The figure below describes the write operation.
Figure 1. Write Access Ordered by a Master
Notes:
- 1.When SVACC is low, the state of SVREAD becomes irrelevant.
- 2.RXRDY is set when data has been transmitted from the internal shifter to TWIHS_RHR and reset when this data is read.