64-lead Package Pinout

Table 1. 64-lead Package Pinout
LQFP Pin	QFN Pin (11)	Power Rail	I/O Type	Primary		Alternate		PIO Peripheral A		PIO Peripheral B		PIO Peripheral CDir		PIO Peripheral DDir		Reset State
LQFP Pin	QFN Pin (11)	Power Rail	I/O Type	Signal	Dir	Signal	Dir	Signal	Dir	Signal	Dir	Signal	Dir	Signal	Dir	Signal, Dir, PU, PD, HiZ, ST
40	40	VDDIO	GPIO_AD	PA3	I/O	PIODC0⁽¹⁾	I	TWD0⁽²⁾	I/O	LONCOL1	I	PCK2	O	–	–	PIO, I, PU, ST
34	34	VDDIO	GPIO	PA4	I/O	WKUP3/PIODC1⁽²⁾	I	TWCK0	O	TCLK0	I	UTXD1	O	–	–	PIO, I, PU, ST
32	32	VDDIO	GPIO_AD	PA5	I/O	WKUP4/PIODC2⁽²⁾	I	PWMC1_PWML3	O	ISI_D4	I	URXD1	I	–	–	PIO, I, PU, ST
15	15	VDDIO	CLOCK	PA7	I/O	XIN32⁽³⁾	I	–	–	PWMC0_PWMH3	–	–	–	–	–	PIO, HiZ
16	16	VDDIO	CLOCK	PA8	I/O	XOUT32⁽³⁾	O	PWMC1_PWMH3	O	AFE0_ADTRG	I	–	–	–	–	PIO, HiZ
33	33	VDDIO	GPIO_AD	PA9	I/O	WKUP6/PIODC3⁽²⁾	I	URXD0	I	ISI_D3	I	PWMC0_PWM FI0	I	–	–	PIO, I, PU, ST
28	28	VDDIO	GPIO_AD	PA10	I/O	PIODC4⁽¹⁾	I	UTXD0	O	PWMC0_PWMEXT RG0	I	RD	I	–	–	PIO, I, PU, ST
27	27	VDDIO	GPIO_AD	PA11	I/O	WKUP7/PIODC5⁽²⁾	I	QCS	O	PWMC0_PWMH0	O	PWMC1_PWM L0	O	–	–	PIO, I, PU, ST
29	29	VDDIO	GPIO_AD	PA12	I/O	PIODC6⁽¹⁾	I	QIO1	I/O	PWMC0_PWMH1	O	PWMC1_PWM H0	O	–	–	PIO, I, PU, ST
18	18	VDDIO	GPIO_AD	PA13	I/O	PIODC7⁽¹⁾	I	QIO0	I/O	PWMC0_PWMH2	O	PWMC1_PWM L1	O	–	–	PIO, I, PU, ST
19	19	VDDIO	GPIO_CLK	PA14	I/O	WKUP8/PIODCEN 1⁽²⁾	I	QSCK	O	PWMC0_PWMH3	O	PWMC1_PWM H1	O	–	–	PIO, I, PU, ST
12	12	VDDIO	GPIO_AD	PA21	I/O	AFE0_AD1/ PIODCEN2⁽⁷⁾	I	RXD1	I	PCK1	O	PWMC1_PWM FI0	I	–	–	PIO, I, PU, ST
17	17	VDDIO	GPIO_AD	PA22	I/O	PIODCCLK⁽¹⁾	I	RK	I/O	PWMC0_PWMEXT RG1	I	–	O	–	–	PIO, I, PU, ST
23	23	VDDIO	GPIO_AD	PA24	I/O	–	–	RTS1	O	PWMC0_PWMH1	O	A20	O	ISI_PCK	I	PIO, I, PU, ST
30	30	VDDIO	GPIO_AD	PA27	I/O	–	–	DTR1	O	TIOB2	I/O	–	I/O	ISI_D7	I	PIO, I, PU, ST
8	8	VDDIO	GPIO	PB0	I/O	AFE0_AD10/ RTCOUT0⁽⁶⁾	I	PWMC0_PWMH0	O	–	–	RXD0	I	TF	I/O	PIO, I, PU, ST
7	7	VDDIO	GPIO	PB1	I/O	AFE1_AD0/ RTCOUT1⁽⁶⁾	I	PWMC0_PWMH1	O	GTSUCOMP	O	TXD0	I/O	TK	I/O	PIO, I, PU, ST
9	9	VDDIO	GPIO	PB2	I/O	AFE0_AD5⁽⁴⁾	I	CANTX0	O	–	–	CTS0	I	–	I/O	PIO, I, PU, ST
11	11	VDDIO	GPIO_AD	PB3	I/O	AFE0_AD2/WKUP 12⁽⁶⁾	I	CANRX0	I	PCK2	O	RTS0	O	ISI_D2	I	PIO, I, PU, ST
46	46	VDDIO	GPIO_MLB	PB4	I/O	TDI⁽⁸⁾	I	TWD1	I/O	PWMC0_PWMH2	O	MLBCLK -	I -	TXD1	I/O	PIO, I, PD, ST
47	47	VDDIO	GPIO_MLB	PB5	I/O	TDO/TRACESWO/ WKUP13⁽⁸⁾	O	TWCK1	O	PWMC0_PWML0	O	MLBDAT -	I/O -	TD	O	O, PU
35	35	VDDIO	GPIO	PB6	I/O	SWDIO/TMS⁽⁸⁾	I	–	–	–	–	–	–	–	–	PIO,I,ST
39	39	VDDIO	GPIO	PB7	I/O	SWCLK/TCK⁽⁸⁾	I	–	–	–	–	–	–	–	–	PIO,I,ST
62	63	VDDIO	CLOCK	PB8	I/O	XOUT⁽⁹⁾	O	–	–	–	–	–	–	–	–	PIO, HiZ
63	64	VDDIO	CLOCK	PB9	I/O	XIN⁽⁹⁾	I	–	–	–	–	–	–	–	–	PIO, HiZ
38	38	VDDIO	GPIO	PB12	I/O	ERASE⁽⁸⁾	I	PWMC0_PWML1	O	GTSUCOMP	O	–	–	PCK0	O	PIO, I, PD, ST
1	2	VDDIO	GPIO_AD	PD0	I/O	DAC1⁽¹¹⁾	I	GTXCK	I	PWMC1_PWML0	O	–	I/O	DCD0	I	PIO, I, PU, ST
57	57	VDDIO	GPIO	PD1	I/O	–	–	GTXEN	O	PWMC1_PWMH0	O	–	I/O	DTR0	O	PIO, I, PU, ST
56	56	VDDIO	GPIO	PD2	I/O	–	–	GTX0	O	PWMC1_PWML1	O	–	I/O	DSR0	I	PIO, I, PU, ST
55	55	VDDIO	GPIO	PD3	I/O	–	–	GTX1	O	PWMC1_PWMH1	O	UTXD4	O	RI0	I	PIO, I, PU, ST
54	54	VDDIO	GPIO_CLK	PD4	I/O	–	–	GRXDV	I	PWMC1_PWML2	O	TRACED0	O	–	–	PIO, I, PU, ST
53	53	VDDIO	GPIO_CLK	PD5	I/O	–	–	GRX0	I	PWMC1_PWMH2	O	TRACED1	O	–	–	PIO, I, PU, ST
51	51	VDDIO	GPIO_CLK	PD6	I/O	–	–	GRX1	I	PWMC1_PWML3	O	TRACED2	O	–	–	PIO, I, PU, ST
50	50	VDDIO	GPIO_CLK	PD7	I/O	–	–	GRXER	I	PWMC1_PWMH3	O	TRACED3	O	–	–	PIO, I, PU, ST
49	49	VDDIO	GPIO_CLK	PD8	I/O	–	–	GMDC	O	PWMC0_PWMFI1	I	–	–	TRACECLK	O	PIO, I, PU, ST
48	48	VDDIO	GPIO_CLK	PD9	I/O	–	–	GMDIO	I/O	PWMC0_PWMFI2	I	AFE1_ADTRG	I	–	–	PIO, I, PU, ST
44	44	VDDIO	GPIO_MLB	PD10	I/O	–	–	GCRS	I	PWMC0_PWML0	O	TD	O	MLBSIG -	I/O -	PIO, I, PD, ST
43	43	VDDIO	GPIO_AD	PD11	I/O	–	–	GRX2	I	PWMC0_PWMH0	O	GTSUCOMP	O	ISI_D5	I	PIO, I, PU, ST
41	41	VDDIO	GPIO_AD	PD12	I/O	–	–	GRX3	I	–	O	–	O	ISI_D6	I	PIO, I, PU, ST
26	26	VDDIO	GPIO_AD	PD21	I/O	–	–	PWMC0_PWMH1	O	–	I/O	TIOA11	I/O	ISI_D1	I	PIO, I, PU, ST
25	25	VDDIO	GPIO_AD	PD22	I/O	–	–	PWMC0_PWMH2	O	–	O	TIOB11	I/O	ISI_D0	I	PIO, I, PU, ST
22	22	VDDIO	GPIO_AD	PD24	I/O	–	–	PWMC0_PWML0	O	RF	I/O	TCLK11	I	ISI_HSYNC	I	PIO, I, PU, ST
20	20	VDDIO	GPIO_AD	PD25	I/O	–	–	PWMC0_PWML1	O	–	I/O	URXD2	I	ISI_VSYNC	I	PIO, I, PU, ST
21	21	VDDIO	GPIO	PD26	I/O	–	–	PWMC0_PWML2	O	TD	O	UTXD2	O	UTXD1	O	PIO, I, PU, ST
2	3	VDDIO	GPIO_AD	PD31	I/O	–	–	QIO3	I/O	UTXD3	O	PCK2	O	ISI_D11	I	PIO, I, PU, ST
3	4	VDDOUT	Power	VDDOUT	–	–	–	–	–	–	–	–	–	–	–	–
4	5	VDDIN	Power	VDDIN	–	–	–	–	–	–	–	–	–	–	–	–
5	6	VDDIO	Reference	VREFP	I	–	–	–	–	–	–	–	–	–	–	–
36	36	VDDIO	RST	NRST	I/O	–	–	–	–	–	–	–	–	–	–	PIO, I, PU
37	37	VDDIO	TEST	TST	I	–	–	–	–	–	–	–	–	–	–	I, PD
10, 42, 58	10,42,58	VDDIO	Power	VDDIO	–	–	–	–	–	–	–	–	–	–	–	–
45	45	VDDIO	TEST	JTAGSEL	I	–	–	–	–	–	–	–	–	–	–	I, PD
13, 24, 61	13,24,61	VDDCORE	Power	VDDCOR E	–	–	–	–	–	–	–	–	–	–	–	–
52	52	VDDPLL	Power	VDDPLL	–	–	–	–	–	–	–	–	–	–	–	–
59	59	VDDUTMII	USBHS	DM	I/O	–	–	–	–	–	–	–	–	–	–	–
60	60	VDDUTMII	USBHS	DP	I/O	–	–	–	–	–	–	–	–	–	–	–
14, 31	14,31	GND	Ground	GND	–	–	–	–	–	–	–	–	–	–	–	–
6	-	GND	Ground	GND	-	–	–	–	-	–	-	–	–	–	–	–
64	1	VDDPLLUSB	Power	VDDPLLU SB	–	–	–	–	–	–	–	–	–	–	–	–
--	62	--	VBG	VBG	I	–	–	–	–	–	-	–	–	–	–	–

Notes:

1.To select this extra function, refer to the Parallel Capture Mode section in the Parallel Input/Output Controller (PIO) chapter.
2.PIODCEN1/PIODCx has priority over WKUPx. Refer to the Parallel Capture Mode section in the PIO chapter.
3.Refer to the Slow Clock Generator section in the Supply Controller (SUPC) chapter.
4.To select this extra function, refer to the I/O Lines section in the External Bus Interface (EBI) chapter. This selection is independent of the PIO line configuration. PIO lines must be configured according to required settings (PU or PD).
5.Analog input has priority over WKUPx pin. To select the analog input, refer to the I/O Lines section in the EBI chapter. WKUPx can be used if the PIO controller defines the I/O line as “input”.
6.Analog input has priority over RTCOUTx pin. To select the analog input, refer to the I/O Lines section in the EBI chapter. Refer to the Waveform Generation section in the Real-Time Clock (RTC) chapter to select RTCOUTx.
7.Analog input has priority over WKUPx pin. To select the analog input, refer to the I/O Lines section in the EBI chapter. To select PIODCEN2, refer to the Parallel Capture Mode in the PIO chapter.
8.Refer to the System I/O Configuration Register (CCFG_SYSIO) in the Bus Matrix (MATRIX) chapter.
9.Refer to the Main Crystal Oscillator section in the Clock Generator chapter. This selection is independent of the PIO line configuration. PIO lines must be configured according to XINxx (I) and XOUTxx (O).
10.DAC0 is selected when DACC_CHER.CH0 is set. DAC1 is selected when DACC_CHER.CH1 is set. Refer to the DACC Channel Enable Register in the Digital-to-Analog Converter Controller (DACC) chapter.
11.The exposed pad of the QFN64 package MUST be connected to ground.