PWM_IER2

PWM Interrupt Enable Register 2

This register can only be written if bits WPSWS1 and WPHWS1 are cleared in the PWM Write Protection Status Register.

  0x34 32 Write-only –  
Parent topic: Register Summary

PWM Interrupt Enable Register 2

Bit  31 30 29 28 27 26 25 24  
                   
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
  CMPU7 CMPU6 CMPU5 CMPU4 CMPU3 CMPU2 CMPU1 CMPU0  
Access  W W W W W W W W  
Reset  0 0 0 0 0 0 0 –  
Bit  15 14 13 12 11 10 9 8  
  CMPM7 CMPM6 CMPM5 CMPM4 CMPM3 CMPM2 CMPM1 CMPM0  
Access  W W W W W W W W  
Reset  0 0 0 0 0 0 0 –  
Bit  7 6 5 4 3 2 1 0  
          UNRE     WRDY  
Access          W     W  
Reset          –     –  

Bit 0 – WRDY: Write Ready for Synchronous Channels Update Interrupt Enable

Write Ready for Synchronous Channels Update Interrupt Enable

Bit 3 – UNRE: Synchronous Channels Update Underrun Error Interrupt Enable

Synchronous Channels Update Underrun Error Interrupt Enable

Bits 8, 9, 10, 11, 12, 13, 14, 15 – CMPMx: Comparison x Match Interrupt Enable

Comparison x Match Interrupt Enable

Bits 16, 17, 18, 19, 20, 21, 22, 23 – CMPUx: Comparison x Update Interrupt Enable

Comparison x Update Interrupt Enable