UART Control Register
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| REQCLR | RSTSTA | ||||||||
| Access | W | W | |||||||
| Reset | – | – |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TXDIS | TXEN | RXDIS | RXEN | RSTTX | RSTRX | ||||
| Access | W | W | W | W | W | W | |||
| Reset | – | – | – | – | – | – |
Reset Receiver
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | The receiver logic is reset and disabled. If a character is being received, the reception is aborted. |
Reset Transmitter
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | The transmitter logic is reset and disabled. If a character is being transmitted, the transmission is aborted. |
Receiver Enable
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | The receiver is enabled if RXDIS is 0. |
Receiver Disable
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | The receiver is disabled. If a character is being processed and RSTRX is not set, the character is completed before the receiver is stopped. |
Transmitter Enable
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | The transmitter is enabled if TXDIS is 0. |
Transmitter Disable
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | The transmitter is disabled. If a character is being processed and a character has been written in the UART_THR and RSTTX is not set, both characters are completed before the transmitter is stopped. |
Reset Status
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Resets the status bits PARE, FRAME, CMP and OVRE in the UART_SR. |
Request Clear
0: No effect.
1: Bit REQCLR clears the potential clock request currently issued by UART, thus the potential system wake-up is cancelled.
0: No effect.
1: Bit REQCLR restarts the comparison trigger to enable receive holding register loading.