The transmitter and the receiver can be programmed to operate with
the clock signals provided on either the TK or RK pins. This allows the SSC to support many
Slave mode data transfers. In this case, the maximum clock speed allowed on the RK pin
is:
- Peripheral clock divided by 2 if Receive Frame Synchronization is input
- Peripheral clock divided by 3 if Receive Frame Synchronization is output
In addition, the maximum clock speed allowed on the TK pin is:
- Peripheral clock divided by 6 if Transmit Frame Synchronization is input
- Peripheral clock divided by 2 if Transmit Frame Synchronization is output
These are only theoretical speed limits for first order calculations. Exact speed limits on
TK and RK are provided in the "Electrical Characteristics" chapter.