XDMAC_GSWF

XDMAC Global Channel Software Flush Request Register

  0x40 32 Write-only  

XDMAC Global Channel Software Flush Request Register

Bit  31 30 29 28 27 26 25 24  
                   
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
  SWF23 SWF22 SWF21 SWF20 SWF19 SWF18 SWF17 SWF16  
Access  W W W W W W W W  
Reset   
Bit  15 14 13 12 11 10 9 8  
  SWF15 SWF14 SWF13 SWF12 SWF11 SWF10 SWF9 SWF8  
Access  W W W W W W W W  
Reset   
Bit  7 6 5 4 3 2 1 0  
  SWF7 SWF6 SWF5 SWF4 SWF3 SWF2 SWF1 SWF0  
Access  W W W W W W W W  
Reset   

Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 – SWFx: XDMAC Channel x Software Flush Request

XDMAC Channel x Software Flush Request

ValueDescription
0

No effect.

1

Requests a DMA transfer flush for channel x. This bit is only relevant when the transfer is source peripheral synchronized.