TC_QIMR

TC QDEC Interrupt Mask Register

  0xD0 32 Read-only 0x00000000  
Parent topic: Register Summary

TC QDEC Interrupt Mask Register

Bit  31 30 29 28 27 26 25 24  
                   
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
                   
Access                   
Reset                   
Bit  15 14 13 12 11 10 9 8  
                   
Access                   
Reset                   
Bit  7 6 5 4 3 2 1 0  
          MPE QERR DIRCHG IDX  
Access          R R R R  
Reset          0 0 0 0  

Bit 0 – IDX: Index

Index

ValueDescription
0 The interrupt on IDX input is disabled.
1 The interrupt on IDX input is enabled.

Bit 1 – DIRCHG: Direction Change

Direction Change

ValueDescription
0 The interrupt on rotation direction change is disabled.
1 The interrupt on rotation direction change is enabled.

Bit 2 – QERR: Quadrature Error

Quadrature Error

ValueDescription
0 The interrupt on quadrature error is disabled.
1 The interrupt on quadrature error is enabled.

Bit 3 – MPE: Consecutive Missing Pulse Error

Consecutive Missing Pulse Error

ValueDescription
0 The interrupt on the maximum number of consecutive missing pulses specified in MAXCMP is disabled.
1 The interrupt on the maximum number of consecutive missing pulses specified in MAXCMP is enabled.