GMAC_IMRPQx

GMAC Interrupt Mask Register Priority Queue x

A read of this register returns the value of the receive complete interrupt mask.

A write to this register directly affects the state of the corresponding bit in the Interrupt Status Register, causing an interrupt to be generated if a '1' is written.

The following values are valid for all listed bit names of this register:

0: Corresponding interrupt is enabled.

1: Corresponding interrupt is disabled.

  0x0640 + (x-1)*0x04 [x=1..5] 32 Read/Write 0x00000000   5 1index -1

GMAC Interrupt Mask Register Priority Queue x

Bit  31 30 29 28 27 26 25 24  
                   
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
                   
Access                   
Reset                   
Bit  15 14 13 12 11 10 9 8  
          HRESP ROVR      
Access                   
Reset          0 0      
Bit  7 6 5 4 3 2 1 0  
  TCOMP AHB RLEX     RXUBR RCOMP    
Access                   
Reset  0 0 0     0 0    

Bit 1 – RCOMP: Receive Complete

Receive Complete

Bit 2 – RXUBR: RX Used Bit Read

RX Used Bit Read

Bit 5 – RLEX: Retry Limit Exceeded or Late Collision

Retry Limit Exceeded or Late Collision

Bit 6 – AHB: AHB Error

AHB Error

Bit 7 – TCOMP: Transmit Complete

Transmit Complete

Bit 10 – ROVR: Receive Overrun

Receive Overrun

Bit 11 – HRESP: HRESP Not OK

HRESP Not OK