PWM_CMPMUPDx

PWM Comparison x Mode Update Register

This register acts as a double buffer for the CEN, CTR, CPR and CUPR values. This prevents an unexpected comparison x match.

  0x013C + x*0x10 [x=0..7] 32 W –   8 16 -1

PWM Comparison x Mode Update Register

Bit  31 30 29 28 27 26 25 24  
                   
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
          CUPRUPD[3:0]  
Access          W W W W  
Reset          0 0 0  
Bit  15 14 13 12 11 10 9 8  
          CPRUPD[3:0]  
Access          W W W W  
Reset          0 0 0  
Bit  7 6 5 4 3 2 1 0  
  CTRUPD[3:0]       CENUPD  
Access  W W W W       W  
Reset  0 0 0        

Bit 0 – CENUPD: Comparison x Enable Update

Comparison x Enable Update

ValueDescription
0

The comparison x is disabled and can not match.

1

The comparison x is enabled and can match.

Bits 7:4 – CTRUPD[3:0]: Comparison x Trigger Update

Comparison x Trigger Update

The comparison x is performed when the value of the comparison x period counter (CPRCNT) reaches the value defined by CTR.

Bits 11:8 – CPRUPD[3:0]: Comparison x Period Update

Comparison x Period Update

CPR defines the maximum value of the comparison x period counter (CPRCNT). The comparison x value is performed periodically once every CPR+1 periods of the channel 0 counter.

Bits 19:16 – CUPRUPD[3:0]: Comparison x Update Period Update

Comparison x Update Period Update

Defines the time between each update of the comparison x mode and the comparison x value. This time is equal to CUPR+1 periods of the channel 0 counter.