USBHS_HSTISR

Host Global Interrupt Status Register

  0x0404 32 Read-only 0x00000000  
Parent topic: Register Summary

Host Global Interrupt Status Register

Bit  31 30 29 28 27 26 25 24  
  DMA_6 DMA_5 DMA_4 DMA_3 DMA_2 DMA_1 DMA_0    
Access                   
Reset  0 0 0 0 0 0 0    
Bit  23 22 21 20 19 18 17 16  
              PEP_9 PEP_8  
Access                   
Reset              0 0  
Bit  15 14 13 12 11 10 9 8  
  PEP_7 PEP_6 PEP_5 PEP_4 PEP_3 PEP_2 PEP_1 PEP_0  
Access                   
Reset  0 0 0 0 0 0 0 0  
Bit  7 6 5 4 3 2 1 0  
    HWUPI HSOFI RXRSMI RSMEDI RSTI DDISCI DCONNI  
Access                   
Reset    0 0 0 0 0 0 0  

Bit 0 – DCONNI: Device Connection Interrupt

Device Connection Interrupt

ValueDescription
0

Cleared when USBHS_HSTICR.DCONNIC = 1.
1

Set when a new device has been connected to the USB bus.

Bit 1 – DDISCI: Device Disconnection Interrupt

Device Disconnection Interrupt

ValueDescription
0

Cleared when USBHS_HSTICR.DDISCIC = 1.
1

Set when the device has been removed from the USB bus.

Bit 2 – RSTI: USB Reset Sent Interrupt

USB Reset Sent Interrupt

ValueDescription
0

Cleared when USBHS_HSTICR.RSTIC = 1.
1

Set when a USB Reset has been sent to the device.

Bit 3 – RSMEDI: Downstream Resume Sent Interrupt

Downstream Resume Sent Interrupt

ValueDescription
0

Cleared when USBHS_HSTICR.RSMEDIC = 1.
1

Set when a Downstream Resume has been sent to the device.

Bit 4 – RXRSMI: Upstream Resume Received Interrupt

Upstream Resume Received Interrupt

ValueDescription
0

Cleared when USBHS_HSTICR.RXRSMIC = 1.
1

Set when an Upstream Resume has been received from the device.

Bit 5 – HSOFI: Host Start of Frame Interrupt

Host Start of Frame Interrupt

ValueDescription
0

Cleared when USBHS_HSTICR.HSOFIC = 1.
1

Set when a SOF is issued by the host controller. This triggers a USB interrupt when HSOFE = 1. When using the host controller in Low-speed mode, this bit is also set when a keep-alive is sent.

Bit 6 – HWUPI: Host Wakeup Interrupt

Host Wakeup Interrupt

This bit is set when the host controller is in Suspend mode (SOFE = 0) and an upstream resume from the peripheral is detected.

This bit is set when the host controller is in Suspend mode (SOFE = 0) and a peripheral disconnection is detected.

This interrupt is generated even if the clock is frozen by the USBHS_CTRL.FRZCLK bit.

Bits 8, 9, 10, 11, 12, 13, 14, 15, 16, 17 – PEP_: Pipe x Interrupt

Pipe x Interrupt

ValueDescription
0

Cleared when the interrupt source is served.
1

Set when an interrupt is triggered by pipe x (USBHS_HSTPIPISRx). This triggers a USB interrupt if the corresponding bit in USBHS_HSTIMR = 1.

Bits 25, 26, 27, 28, 29, 30, 31 – DMA_: DMA Channel x Interrupt

DMA Channel x Interrupt

ValueDescription
0

Cleared when the USBHS_HSTDMASTATUSx interrupt source is cleared.
1

Set when an interrupt is triggered by the DMA channel x. This triggers a USB interrupt if the corresponding bit in USBHS_HSTIMR = 1.