PIO_PCIER

PIO Parallel Capture Interrupt Enable Register

The following configuration values are valid for all listed bit names of this register:

0: No effect

1: Enables the corresponding interrupt

  0x0154 32 Write-only    
Parent topic: Parallel Input/Output Controller (PIO) User Interface

PIO Parallel Capture Interrupt Enable Register

Bit  31 30 29 28 27 26 25 24  
                   
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
                   
Access                   
Reset                   
Bit  15 14 13 12 11 10 9 8  
                   
Access                   
Reset                   
Bit  7 6 5 4 3 2 1 0  
          RXBUFF ENDRX OVRE DRDY  
Access                   
Reset                   

Bit 0 – DRDY: Parallel Capture Mode Data Ready Interrupt Enable

Parallel Capture Mode Data Ready Interrupt Enable

Bit 1 – OVRE: Parallel Capture Mode Overrun Error Interrupt Enable

Parallel Capture Mode Overrun Error Interrupt Enable

Bit 2 – ENDRX: End of Reception Transfer Interrupt Enable

End of Reception Transfer Interrupt Enable

Bit 3 – RXBUFF: Reception Buffer Full Interrupt Enable

Reception Buffer Full Interrupt Enable