QSPI_TDR

QSPI Transmit Data Register

  0x0C 32 Write-only –  

QSPI Transmit Data Register

Bit  31 30 29 28 27 26 25 24  
                   
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
                   
Access                   
Reset                   
Bit  15 14 13 12 11 10 9 8  
  TD[15:8]  
Access  W W W W W W W W  
Reset  0 0 0 0 0 0 0 0  
Bit  7 6 5 4 3 2 1 0  
  TD[7:0]  
Access  W W W W W W W W  
Reset  0 0 0 0 0 0 0  

Bits 15:0 – TD[15:0]: Transmit Data

Transmit Data

Data to be transmitted by the QSPI is stored in this register. Information to be transmitted must be written to the Transmit Data register in a right-justified format.