USBHS_HSTPIPIERx

Host Pipe x Enable Register (Control, Bulk Pipes)

This register view is relevant only if PTYPE = 0x0 or 0x2 in ”Host Pipe x Configuration Register”.

For additional information, see ”Host Pipe x Mask Register (Control, Bulk Pipes)”.

This register always reads as zero.

The following configuration values are valid for all listed bit names of this register:

0: No effect.

1: Sets the corresponding bit in USBHS_HSTPIPIMRx.

  0x05F0 + x*0x04 [x=0..9] 32 Read/Write 0   10 x
Parent topic: Register Summary

Host Pipe x Enable Register (Control, Bulk Pipes)

Bit  31 30 29 28 27 26 25 24  
                   
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
            RSTDTS PFREEZES PDISHDMAS  
Access                   
Reset            0 0 0  
Bit  15 14 13 12 11 10 9 8  
        NBUSYBKES          
Access                   
Reset        0          
Bit  7 6 5 4 3 2 1 0  
  SHORTPACKETIES RXSTALLDES OVERFIES NAKEDES PERRES TXSTPES TXOUTES RXINES  
Access                   
Reset  0 0 0 0 0 0 0 0  

Bit 0 – RXINES: Received IN Data Interrupt Enable

Received IN Data Interrupt Enable

Bit 1 – TXOUTES: Transmitted OUT Data Interrupt Enable

Transmitted OUT Data Interrupt Enable

Bit 2 – TXSTPES: Transmitted SETUP Interrupt Enable

Transmitted SETUP Interrupt Enable

Bit 3 – PERRES: Pipe Error Interrupt Enable

Pipe Error Interrupt Enable

Bit 4 – NAKEDES: NAKed Interrupt Enable

NAKed Interrupt Enable

Bit 5 – OVERFIES: Overflow Interrupt Enable

Overflow Interrupt Enable

Bit 6 – RXSTALLDES: Received STALLed Interrupt Enable

Received STALLed Interrupt Enable

Bit 7 – SHORTPACKETIES: Short Packet Interrupt Enable

Short Packet Interrupt Enable

Bit 12 – NBUSYBKES: Number of Busy Banks Enable

Number of Busy Banks Enable

Bit 16 – PDISHDMAS: Pipe Interrupts Disable HDMA Request Enable

Pipe Interrupts Disable HDMA Request Enable

Bit 17 – PFREEZES: Pipe Freeze Enable

Pipe Freeze Enable

Bit 18 – RSTDTS: Reset Data Toggle Enable

Reset Data Toggle Enable