ERASE Pin

The ERASE pin is used to perform hardware erase of the on-chip Flash and the NVM bits including GPNVM bits, Lock bits and the Security Bit. The hardware erase sequence will first erase the entire Flash and afterwards the NVM bits in order to fully secure the content of the on-chip Flash. The ERASE pin integrates a pulldown resistor of about 100 kΩ to GND, so that it can be left unconnected for normal operations.

The ERASE pin is a system I/O pin that can be used as a standard I/O. At startup, this system I/O pin defaults to the ERASE function. This pin is debounced by SLCK to improve the glitch tolerance. To avoid unexpected erase at power-up due to glitches, a minimum ERASE pin assertion time is required. This time is defined in Table 1.

The erase operation cannot be performed when the system is in Wait mode.

If the ERASE pin is used as a standard I/O in Input or Output mode, note the following considerations and behavior:

• I/O Input mode: At startup of the device, the logic level of the pin must be low to prevent unwanted erasing until the user application has reconfigured this system I/O pin to a standard I/O pin.
• I/O Output mode: asserting the pin to low does not erase the Flash

During software application development, a faulty software may put the device into a deadlock. This may be due to:

• Programming an incorrect clock switching sequence
• Using this system I/O pin as a standard I/O pin
• Entering Wait mode without any wakeup events programmed

To recover normal behavior is to erase the Flash by following the steps below:

1. Apply a logic “1” level on the ERASE pin.

2. Apply a logic “0” level on the NRST pin.

3. Power-down, and then power-up the device.

4. Maintain the ERASE pin to logic “1” level for at least the minimum assertion time after releasing the NRST pin to logic “1” level.